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Panasonic FP-E - Page 491

Panasonic FP-E
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High−level Instructions
3 − 227
Outline Shifts in data to the smallest address of the specified data table and
compresses the data in the table toward the higher address.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P99 (PCMPW)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F99 CMPW, DT10 , DT 0 , DT 5
S
D2
Trigger
D1
R0
10
11
ST R 0
F 99 (CMPW)
DT 10
DT 0
DT 5
S 16-bit equivalent constant or 16-bit area for storing shift−in data
D1 Starting 16-bit area of the data table
D2 Ending 16-bit area of the data table
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
IX
(*2)
IY
(*3)
K H
Index
modifier
S A A A A A A A A A A A A A A
D1 N/A A A A A A A A A N/A N/A N/A N/A A
D2 N/A A A A A A A A A N/A N/A N/A N/A A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
(*2) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
F99
P99
(PCMPW)
(CMPW)
Data table shift−in and compress
A: Available
N/A: Not Available
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