High−level Instructions
3 − 232
Outline Shifts a specified number of bits to the left in bit units.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P101 (PSHL)” is not available.
Program example
Boolean
Ladder Diagram
Address Instruction
10
F101 SHL , DT 0 , K 4
n
D
Trigger
R0
10
11
ST R 0
F101 (SHL)
DT 0
K4
D 16-bit area to be shifted to the left
n 16-bit equivalent constant or 16-bit area (specifies number of shifted bits)
Operands
modifier
D N/A A A A A A A A A A A N/A N/A A
n A A A A A A A A A A A A A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Shifts 4 bits in data register DT0 to the left when trigger R0 turns on.
The data in bit position 12 is transferred to special internal relay R9009 (carry flag).
11 10 01 00
·
·
··
Bit position
·····
DT0
15
101
12
0
11
011
8
0
7
110
4
0
3
101
0
1
·
·
··
Bit position
·····
DT0
15
0
12
0
11
1
8
0
7
1
4
1
3
0
0
0
In this case, the lower
4 bits of DT0 are filled with 0s.
The data in bit position 12
is transferred to R9009
(carry flag).
F101
P101
(PSHL)
(SHL)
Left shift of multiple bits (n bits) in a 16−bit data
A: Available
N/A: Not Available
To Next Page