Panasonic FP-E - Page 498

High−level Instructions
3 − 234
Outline Shifts a specified number of bits to the right in bit units.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P102 (PDSHR)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
F102 DSHR, DT10, DT 2
10
R0
nD
Trigger
10
11
ST R 0
F102 (DSHR)
DT 10
DT 2
D Lower 16-bit area of 32-bit data area to be shifted to the right
n 16-bit equivalent constant or 16-bit area (specifies number of shifted bits)
Range of n: K0 to K255 (H0 to HFF)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Inte
g
er
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
I K H f
Index
modifier
Integer
device
D N/A A A A A A A A A A N/A N/A N/A A N/A
n A A A A A A A A A A A A N/A A N/A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
F102
P102
(PDSHR)
(DSHR)
Right shift of n bits in a 32-bit data
A
:
A
vailable
N/A: Not Available
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