Panasonic FP-E - Page 502

High−level Instructions
3 − 238
Outline Shifts one hexadecimal digit (4 bits) of the specified 16-bit data to the
right.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P105 (PBSR)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F105 BSR , DT 0
D
Trigger
R0
10
11
ST R 0
F105 (BSR)
DT 0
D 16-bit area to be shifted to the right
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Shifts one hexadecimal digit (4 bits) in data register DT0 to the right when trigger R0 turns on.
The data in hexadecimal digit position 1 (bit positions 0 to 3) is shifted out and transferred to the lower digit
position (bit positions 0 to 3) of special data register DT9014 (with the FP0 T32, FPΣ,FP−X, FP2, FP2SH and
FP10SH: DT90014).
00 00 00
00 00 00
0009
1001
9
····
Bit position
·····
Binary
15
1
12
1
11
1
8
1
7
1
4
1
3
100
0
1
R0: on
9999
Hexadecimal
DT0
·· ·
Bit position
·····
Binary
15
0
12
0
11
1
8
1
7
1
4
1
30
099
Hexadecimal
DT0
·· ·
Bit position
·····
Binary
15
000
12
0
11
000
8
0
7
000
4
0
3
100
0
1
Hexadecimal
DT9014/
DT90014
(H9999)
(H999)
(H9)
F105
P105
(PBSR)
(BSR)
Right shift of one hexadecimal digit (4 bits)
A: Available
N/A: Not Available
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