Panasonic FP-E - Page 508

High−level Instructions
3 − 244
Outline Shifts multiple bits of a specified 16-bit data range to the left.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P109 (PBITL)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
Trigger
nD1 D2
F109 BITL, DT10, DT12, K 410
R0
10
11
ST R 10
F109 (BITL)
DT 10
DT 12
K4
D1 Starting 16-bit area
D2 Ending 16-bit area
n 16-bit equivalent constant or 16-bit area to specify number of shifted bits
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Inte
g
er
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
I K H f
Index
modifier
Integer
device
D1 N/A A A A A A A A A A N/A N/A N/A A N/A
D2 N/A A A A A A A A A A N/A N/A N/A A N/A
n A A A A A A A A A A A A N/A A N/A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
Explanation of example
Shifts 4 bits in the data range (3 words) from DT10 through DT12 to the left when trigger R0 turns on.
DT12 DT11
H2320
The 4 bits in DT12
are shifted out.
H0212
DT10
3 words
H0030 H0232
H0300H2120
The 4 bits in data
becomes 0.
F109
P109
(PBITL)
(BITL)
Left shift of multiple bits of 16-bit data range
A
:
A
vailable
N/A: Not Available
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