Panasonic FP-E - Page 516

High−level Instructions
3 − 252
Outline Shifts one hexadecimal digit (4 bits) of a specified 16-bit data range to
the left.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P113 (PWBSL)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F113 WBSL , DT 0 , DT 9
D1
Trigger
R0
D2
10
11
ST R 0
F113 (WBSL)
DT 0
DT 9
D1 Starting 16-bit area
D2 Ending 16-bit area
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
I K H
Index
modifier
D1 N/A A A A A A A A A N/A N/A N/A A
D2 N/A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
Explanation of example
Shifts one hexadecimal digit (4 bits) of the data range (10 words) from DT0 through DT9 to the left when
trigger R0 turns on.
02
R0: on
The data “0” in the
higher hexadecimal
digit (bit positions 12
to 15) is shifted out.
Specified data range (10 words = 40 digits)
121 0232
·· ·· · · · ·
15 1211 8 7 4 3 0
DT9
·· ·· ·· · ·
15 1211 8 7 4 3 0
DT0
22102320
·· ·· · · · ·
15 1211 8 7 4 3 0
DT9
·······
15 1211 8 7 4 3 0
DT0
··
15
··
15
··
0
··
0
1
The lower hexadecimal digit
(bit position 0 to 3) becomes 0.
F113
P113
(PWBSL)
(WBSL)
Left shift of one hexadecimal digit (4−bit)
of 16-bit data range
A: Available
N/A: Not Available
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