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Panasonic FP-E - Page 520

Panasonic FP-E
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High−level Instructions
3 − 256
Outline Reads data from the FIFO buffer.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P116 (PFIFR)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
F116 FIFR, DT 0, DT 10010
R10
DF
D
S
Trigger
10
11
12
ST R 10
DF
F116 (FIFR)
DT 0
DT 100
S Starting 16-bit area of FIFO buffer
D 16-bit area for storing data read from FIFO buffer
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
IX
(*2)
IY
(*3)
K H
Index
modifier
S N/A A A A A A A A A N/A N/A N/A N/A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
(*2) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
F116
P116
(PFIFR)
(FIFR)
Data read from FIFO buffer
A: Available
N/A: Not Available
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