Panasonic FP-E - Page 531

High−level Instructions
3 − 267
Outline Sets the UP/DOWN counter.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
R1
F118 UDC
R0
50
Y50
UP/DOWN input
51
R2
Reset input
52
DT 10
DT 0
Count input
S
D
=, DT 0, K 0
50
51
52
53
58
63
ST R 0
ST R 1
ST R 2
F118 (UDC)
DT 10
DT 0
ST=
DT 0
K0
OT Y 50
S 16-bit equivalent constant or 16-bit area for counter preset
value
D 16-bit area for counter elapsed value
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
I K H
Index
modifier
S A A A A A A A A A N/A A A N/A
D N/A A A A A A A A A N/A N/A N/A N/A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
UP/DOWN counter
F118
(UDC)
A: Available
N/A: Not Available
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