Panasonic FP-E - Page 544

High−level Instructions
3 − 280
Outline Rotates a specified number of bits in the specified 16-bit data to the left
together with carry flag data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P123 (PRCL)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F123 RCL , DT 0 , K 4
D
n
Trigger
R0
10
11
ST R 0
F123 (RCL)
DT 0
K4
D 16-bit area
n 16-bit equivalent constant or 16-bit area to specify number of bits to be rotated
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A A N/A N/A A
n A A A A A A A A A A A A A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Rotates 4 bits in data register DT0 together with carry flag data “1” to the left when trigger R0 turns on.
01 01 10 00
R0: on
·· ·
Bit position
·····
DT0
15
0
12
0
11
0
8
1
7
0
4
0
3
1
0
0
Data in bit position 12
Carry flag data “1”
1
Special internal relay
R9009 (carry flag)
····
Bit position
·····
DT0
15
000
12
1
11
001
8
0
7
001
4
1
3
010
0
0
F123
P123
(PRCL)
(RCL)
16-bit data left rotation with carry flag data
A: Available
N/A: Not Available
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