Panasonic FP-E - Page 552

High−level Instructions
3 − 288
Outline Rotates a specified number of bits in the specified 32-bit data to the left
together with carry flag data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P128 (PDRCL)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
F128 DRCL, DT10, K410
R0
nD
Trigger
10
11
ST R 0
F128 (DRCL)
DT 10
K4
D Lower 16-bit area of 32-bit data
n 16-bit equivalent constant or 16-bit area to specify number of bits to be rotated
Range of n: K0 to K255 (H0 to HFF)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Inte
g
er
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
I K H f
Index
modifier
Integer
device
D N/A A A A A A A A A A N/A N/A N/A A N/A
n A A A A A A A A A A A A N/A A N/A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
Explanation of example
Rotates 4 bits in data registers DT11 and DT10 together with carry flag data to the left when trigger R0 turns
on.
The data in bit position 28 is transferred to carry flag (special internal relay R9009).
The data of the carry flag is transferred to the bit position 3.
101 1100 1011
31 0
1100 1101
Carry flag
28 27 24 23 4 3
···
1011
0
@
Carry flag
1
@
0
[DT11, DT10]
[DT11, DT10]
R0: on
F128
P128
(PDRCL)
(DRCL)
32-bit data left rotation with carry flag data
A
:
A
vailable
N/A: Not Available
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