Panasonic FP-E - Page 556

High−level Instructions
3 − 292
Outline Turns off a specified bit of 16-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P131 (PBTR)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F131 BTR , DT 0 , DT 2
D
n
Trigger
R0
10
11
ST R 0
F131 (BTR)
DT 0
DT 2
D 16-bit area
n 16-bit equivalent constant or 16-bit area to specify bit position
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A A N/A N/A A
n A A A A A A A A A A A A A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Turns off the bit specified by DT2 of data register DT0 when trigger R0 turns on.
When the DT2 = K7, as shown below.
10 10 01 01
····
Bit position
·····
DT0
15
110
12
1
11
110
8
0
7
101
4
1
3
101
0
0
R0: on
·· ·
Bit position
·····
DT0
15
1
12
1
11
1
8
0
7
0
4
1
3
1
0
0
[D]
[D]
[n] DT2: K7
Bit position 7 is turned off (0) when R0 turns on.
(Bits other than the specified bit do not change.)
F131
P131
(PBTR)
(BTR)
16-bit data bit reset
A: Available
N/A: Not Available
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