Panasonic FP-E - Page 865

High−level Instructions
3 − 601
Outline Converts a specified bit column to a bit line.
For the FP0R/FPΣ/FP−X, the P type high−level instruction “P241
(PLINE)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
S
Trigger
Dn
F241 LINE, DT10, K10, DT20
10
R0
10
11
ST R 0
F241 (LINE)
DT 10
K10
DT 20
S Starting address of area where bit column will be read.
n 16-bit equivalent constant or 16-bit area to specify bit position
D 16-bit area for storing converted data (destination)
Operands
O
p
erand
Relay Timer/Counter Register
Index
register
Constant
Index
modifier
Integer
device
Operand
WX WY WR WL SV EV DT LD FL I K H f
modifier device
S A A A A A A A A A A N/A N/A N/A A N/A
n A A A A A A A A A A A A N/A A N/A
D N/A A A A A A A A A A N/A N/A N/A A N/A
F241
P241
(PLINE)
(LINE)
Bit column to bit line conversion
A
:
A
vailable
N/A: Not Available
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