Panasonic FZ-10 - PROGRAM Track Playback; Managing Saved Track Sequences

Continued (IC120)
Continued (IC120)
Pin
No.
1/0 Pin Name
-··
Comment
Pin
No.
1/0 Pin Name
Comment
88
0 RA9 Address 9
for
the
right
DRAM and
133 I S24
VRAM 31-bit serial
bus
data
24
VRAM (data
bits
[15:
01)
134 I
S27
VRAM 31-bit serial bus
data
27
89
0
RAS
Address 8
for
the
right
DRAM and
135 I S26
VRAM 31-bit serial bus
data
26
VRAM (data
bits
[15:01)
136 I
S9
VRAM 31-bit serial bus
data
9
90
VDD Power supply
137 VDD
Power
supply
91
0
RAO
Address 0
for
the
right
DRAM and
138 I
S8
VRAM 31-bit serial
bus
data
8
VRAM (data
bits
[15:0])
139 I
S11
VRAM 31-bit serial bus
data
11
92 0
RA7
Address 7
for
the
right
DRAM and
140 I S10
VRAM 31-bit serial
bus
data
10
VRAM (data
bits
[15:01)
141
I
S29
VRAM 31-bit serial
bus
data
29
93 0
RA1
Address 1
for
the
right
DRAM and
VRAM (data
bits
[15:01)
94 GND
Ground
95 0
RA6 Address 6
for
the
right
DRAM and
VRAM (data
bits
[15:0])
96
0
RA2 Address 2
for
the
right
DRAM and
VRAM (data
bits
[15:01)
97
0 RA5 Address 5
for
the
right
DRAM and
VRAM (data
bits
[15:01)
142 I S28
VRAM 31-bit serial bus
data
28
143 I
S31
VRAM 31-bit serial bus
data
31
144 I
S30
VRAM 31-bit serial bus
data
30
145 I S13
VRAM 31-bit serial
bus
data
13
146 I S12 VRAM 31-bit serial bus
data
12
147 I S15 VRAM 31-bit serial
bus
data
15
148 I S14
VRAM 31-bit serial
bus
data
14
149 GND Ground
98
VDD Power
supply
99 0
RA3
Address 3
for
the
right
DRAM and
150 GND
Ground
151
1/0
DO
Data
bus
0
VRAM (data
bits
[15:0])
152
1/0
D1
Data bus 1
100 0 RA4 Address 4
for
the
right
DRAM and
153
1/0
D2
Data bus 2
VRAM (data
bits
[15:0])
154
1/0
D3
Data bus 3
101
GND
Ground
155 VDD
Power
supply
102 0 ROMCS1*
ROM
chip
select
signal 1
156
1/0
D4
Data bus 4
103 0
ROMCSO*
ROM
chip
select
signal 0
157
1/0
D5
Data bus 5
104 0
PDCSO*
Slow bus
chip
select
signal 0
158
1/0
D6
Data bus 6
105
VDD Power
supply
159
1/0
D7
Data bus 7
106
0 PDCS2' Slow bus
chip
select signal 1
160
GND Ground
107 0
PDCS3"'
Slow bus
chip
select signal 2
161
1/0
D8
Data bus 8
108
0 SRAMW" SRAM
write
enable
162
1/0
D9
Data bus 9
109
GND
Ground
163
1/0
D10
Data
bus
10
110 0 SRAMR* SRAM
output
enable
164
1/0
D11
Data
bus
11
111
0
PDWR*
Slow bus read enable.
When
165 VDD Power
supply
accessing the ROM, ANVIL uses 166 1/0
D12
Data bus 12
this
signal as address 1
167
1/0
D13
Data bus 13
112 0 PDRD* Slow bus read enable. When
168 1/0
D14
Data bus 14
accessing
the
ROM, ANVIL uses
169 1/0
D15
Data bus 15
this
signal as address 0
170 GND Ground
113
VDD
Power supply
171
1/0
D16
Data bus 16
114 I REF5V Reference voltage
that
allows
172
1/0
D17
Data
bus
17
ANVIL
to
accept 5
volts
signal
inputs
while
operating internally
3.3 volts.
115 I
S17 VRAM 31-bit serial bus
data
17
116 I S16 VRAM 31-bit serial bus
data
16
117 I
S19 VRAM 31-bit serial bus
data
19
118 I S18 VRAM 31-bit serial bus
data
18
119 I
S1
VRAM 31-bit serial bus
data
1
120 I
so
VRAM 31-bit serial bus
data
0
121
I
S3
VRAM 31-bit serial bus
data
3
122 I
S2
VRAM 31-bit serial bus
data
2
123 I
S21
VRAM 31-bit serial bus
data
21
124 I S20 VRAM 31-bit serial bus
data
20
125
GND Ground
126 I
S23 VRAM 31-bit serial bus
data
23
127 I S22 VRAM 31-bit serial bus
data
22
128 I
S5
VRAM 31-bit serial bus
data
5
129 I
S4
VRAM 31-bit serial bus
data
4
130 I
S7
VRAM 31-bit serial bus
data
7
131
I
S6
VRAM 31-bit serial bus
data
6
132 I
S25 VRAM 31-bit serial bus
data
25
173
1/0
D18
Data bus 18
174
1/0
D19
Data·bus 19
175 VDD Power
supply
176 1/0 D20
Data
bus
20
177
1/0
D21
Data bus
21
178
1/0
D22
Data bus 22
179
1/0
D23
Data bus 23
180 GND
Ground
181
1/0
D24
Data bus 24
182
1/0
D25
Data bus 25
183 1/0
D26
Data
bus
26
184 1/0
D27
Data
bus
27
"185
VDD
Power
supply
186
1/0
D28
Data bus 28
187 1/0
D29
Data bus
29
188
1/0
D30
Data bus 30
189
1/0
D31
Data
bus
31
190 GND Ground
191
1/0
ADBIO0 General-purpose 1/0 bus 0
192 1/0 ADBlO1
General-purpose 1/0 bus 1
2-8