Panasonic TH-L32C53T

TH-L32C53T
31
9 Block Diagram
9.1. Main Block Diagram
S5/ S3.3
S3.3
NAND
Flash
1G
ED[7:0]
XNFCE,XNFW
P
NFCLE,NFAL
E
XNFWE,XNFR
E
NANDRYBY
Support
Card
< DTV_XRST
CPU BUS
XECS1
XEAS
ECLK
ESZ1
XEWE1
ERXW
XNMIRQ
XIRQ1
XERE
XEWE0
ESZ0
XEDK
BOOTSW AP
(XRST)
ED[15:0]
NAND-IF
EA[15:1]
DATA
ADR
CTRL
ED[15:0]
EA[7:0],EA[24]
PCOE
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
HSBCLKOUT
HSSYNCOUT
HSVALOUT
HSD OUT[0 :7]
HS0 BCLKIN
HS0 SYNCIN
HS0 VALIN
HS0DIN[0:7]
PCWAIT
PCCD 1
PCCD 2
PCREADY
CI-IF
TS-INTS-OUT
PWM0LP
PWM0LN
PWM0RP
PWM0RN
HS1 BCLKIN
HS1 SYNCIN
HS1 VALIN
HS1DIN[0:7]
ASMCK
ALRCLKO
ABCKO
ASD OUT2
DMD
P-IIC2 (For D MD only)
ADC
DTV Decoder
SIF Decoder
A-SW
(Thru)
IPR INS
V-SW
(Thru)
ADC
DAC
Analog Video
Processor
Video
For m at
Processor
VIF Decoder
I2S
SW
AMP
PWM
SPDIF
SW
A-Chip
CLK
GEN
A-D Chip
Internal BUS
IIC
DMD-IIC0
DMD-IIC1
Tra ns Port Dec oder CPUBUS NAND-IF
Peaks
sLD2
STB3.3
STB1.2
IIC
STM-IIC
Serial
STM-Serial0
STM-Serial1
24.576MHz
STM
STM-D Chip
Communication Re giste r
2
ETHER
KSZ
ETHER_XRST <
MII-IF
COL,CRS,RX CL K
RXD0,RXD1,RXD2,RXD3
RXD V,RXER,TXCLK
TXD0,TXD 1,TXD2,TXD3
TXEN,MDC,MDIO,MDIO_ INTL
PHYRSTL,WAKEUP,WUC
USB
S5
USB
Power SW
USB* VBUS >
< US B*OC
S5
S5
USB
Power SW
USB* VBUS >
< US B*OC
S5
S5
USB Memory
USB -IF
SD-IF
SDXC
S5
SD Reg
SD_PWR_ON >
< SD_COIN_DET
S3.3
ExFAT: ye s
High Speed: no
UHS-I : no
SD-Data-VCC
SDCLK,SDCMD,SDVOLC,
SDDAT[3:0],SDCD,SDWP
<KEY1
POWER KEY
CONTROL PANEL KEY
Cross Stream Switch
D-Chip
IIC
P-IIC0
P-IIC1
(P-IIC2)
P-IIC3
Serial
P-Serial0
P-Serial1
P-UART0
P-UART2
DMD IIC
DMD_IIC
0
DMD_IIC
1
XOR
EEP
STB3.3
EEP
16k
STM
EEP_W P >
For STM
S3.3
EEP
EEPROM_ W P
P-IIC
For Peaks
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI1
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI2
S3.3
ARC Buffe r -SW
ARC_OFF <
Rx*
Rx*
IECOUT
SOUND_VCC
PWM
AMP
LV4923V
DAC
DSP
HDMI
Rx
MUX
x3
ADC
LVDS-Tx
mini-LVDS-Tx
T-CON
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
ASIA,Latin
ELSE: 16k
DDR
DDR-IF x16 DDR-IF x16
S1.5
DDR3+
x16
1G
S1.5
DDR3+
x32
1G
1333Hz
2G-1333Hz
FHD
D-Book6.x Network
MKV decording
LCD
PANEL
LCD
Driver
Driver
Ctrl
EEP
2k
S15.7
P-IIC
T-CON
DCDC
BD 81021MU V
P-IIC
GAMMA
DAC
BU F12840
AVDD_ENB >
PANEL_VCC_ON >
LCD_EEP_WP >
(LPL),LPR,POLL,POLR
CPV,GDATA1,GDATA2
P-IIC
Back Light
INVERTER
or
LED Driver
BL_ON >
BL_SOS <
S3.3
TEMP
SENSOR
P-IIC
S9
INV-LED
Fo r EEFL
PANEL_LED_ON >
S12
Peaks
DCDC
S1.2
S1.5
S1.8 S3.3
STB3.3
STB1.2
STB_XRST
< TV _SOS
AMP/HP MUTE
MONITOROUT M UT E
S12/S5STB5/5V S
Analog
ASIC
AN34043A
OVP
SOS
Safe ty
Circuit
< MON_MUTE
< SP_HP_MUTE
STB3.3V/1.2V _REG
STB5V Res et IC ( STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OC P/ OV P/ TV - S OS
HP_MUTE, EXT_ MUT E
UHS- I_REG
TV _SOS
PW M
3.3/1.8
UHS- 1
REG
S9-REG
S9
(SD-Data-VCC)
< (SDVOLC)
DCDC_EN
DTV_ XRST >
SW_OFF_DET >
XRST POWER_DET
PWM >
PWMA
PWM >
LD
BKSEL
m in i- LV DS 1 56 MHz RGB2 4b it
7pair(6dat a+1clk 156M) Single
CVBS
RGB /YPbPr /CV BS /YC
HS, VS
Audio OUT L/R
Monitor OUT L/R
Monitor Out L/R
Audio Input
Video Input
Analog AV Input
S9/S5
AV- SW
R2A11023FT
(W/O EU)
㻴㻰㻛㼂㻰㻛㻲㻮㻷
㻹㼁㼀㻱
P-IIC
Main Audio L/R
A-Chip V DD
Analog AV Input
R1, G1, B1 , V 1
LIN1_R, LIN1_L
LO1_R, LO1_L
HP1_R, HP1_L
LO2_R, LO2_L
VDAC1
SCART Out L/R
(Audio L/R)
SIFIN
FEAIN
AV2
CVBS
PC
Side
R L
Y/VPbPrR L
S5/ S3.3/ S1.8
D/A TUNER
SCL
SDA
IF_AGC
IFD_OUT1
IFD_OUT2
SIF_OUT
Video_OUT
Re s et
IEC
ENGS9301D5F
DVB-T
DMD_IIC0
Video_OUT (CVBS)
Low-IF
SIF_OUT
< FE_XRST
SOUND_VCC
I2S
AMP
BD5452AM
< KEY3
AV1 / YUV1
AUDIO OUT
2
E
E
E
T
T
T
E
E
E
E
H
H
H
E
E
E
R
R
R
K
S
Z
C
O
L
,
C
R
S
RR
,
R
X
R
R
C
L
K
R
X
R
R
D
0
,
R
X
R
R
D
1
,
R
X
R
R
D
2
,
R
X
R
R
D
3
R
X
R
R
D
V
,
R
X
R
R
E
R
,
T
X
T
T
C
L
K
T
X
T
T
D
0
,
T
X
T
T
D
1
,
T
X
T
D
2
,
T
X
T
T
D
3
T
X
T
T
E
N
,
M
D
C
,
M
D
I
O
,
M
D
I
O
_
I
N
T
L
P
P
P
H
H
H
Y
Y
Y
R
R
R
Y
Y
Y
Y
Y
Y
S
S
S
R
R
R
R
R
R
T
T
T
L
L
L
,
W
W
W
A
A
A
K
K
K
E
E
E
U
U
U
P
P
P
,
W
W
W
U
U
U
C
C
C
S
Only C55D
A
S
AA
M
C
K
A
L
R
C
R
L
K
O
K
K
A
B
C
K
O
KK
A
S
AA
D
O
U
T
2
S
O
U
N
D
_
V
C
C
I
2
S
A
M
P
B
D
5
4
5
2
A
M
Only C55D