Panasonic VDR-D150EB - CCD Drive Block Diagram

VDR-D100EG/VDR-D100EB/VDR-D150E/VDR-D150EB/VDR-D150EF/VDR-D150EG/VDR-D150EP/VDR-D150EE
/VDR-D150GC/VDR-D150GN/VDR-D150GCS/VDR-D150SG/VDR-D152EG/VDR-D158GK
CCD DRIVE BLOCK DIAGRAM
CCD DRIVE BLOCK DIAGRAM
7
10
4
9
13
12
3
2
1
CCD
IMAGE
SENSOR
IC601 (CCD)
FP301
3
FP301
4
FP301
9
FP301
2
FP301
1
FP301
11
FP301
12
FP301
8
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
LEVEL
CHANGE
DRIVE
DRIVE
5
7
8
9
14
13
12
10
19
22
38
39
16
20
21
15
22
23
30
27
31
3
17
18
1
IC304 (CCD V-DRIVE)
IC302 (TIMING SIGNAL GENERATOR)
IC501 (CAMERA SIGNAL PROCESS)
Q601
BUFFER
CCD P.C.B.
MAIN P.C.B.
V1 PULSE
SAMPLING PULSE 1
SAMPLING PULSE 2
CHARGE PULSE 1
V2 PULSE
V3 PULSE
CHARGE PULSE 2
V4 PULSE
SUB CONTROL PULSE
H1 PULSE
H2 PULSE
RESET PULSE
46
10
11
40
9
OB CLAMP PULSE
PGA LATCH
DOUBLE
SAMPLING
HOLD
10BIT A/D
CONVERTER
SERIAL INTERFACE
TIMING GENERATOR
OB CLAMP
REC VIDEO(CAMERA) SIGNAL
1617 33 34 35 1512
12
3
4
FCK
TG CS (L)
TG SERIAL DATA
TG SERIAL CLOCK
A/D CLOCK 1
VD
HD
CAMERA DATA (0-9)
CAMERA DAC/TG SERIAL CLOCK
CAMERA DAC/TG SERIAL DATA
CAMERA DAC CS (L)
FCK (18.0MHz)
CAM HD
CAM VD
8
2FCK
IC303
36MHz
OSC
FROM SYSTEM CONTROL
BLOCK DIAGRAM
TO VIDEO SIGNAL PROCESS
BLOCK DIAGRAM
TG CS (L)
44TG RESET (L) TG RESET (L)
FP301
14
CAMERA DATA (10 BIT)
1
36
9
2.80 Vp-p
1 V
5 ms
V1
TO VIDEO SIGNAL PROCESS
BLOCK DIAGRAM