CPU & PCI Bus Control
This item has several sub-items:
PCI 1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait
states, providing faster data transfer.
PCI 1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to
compensate for the speed differences between the CPU and PCI
bus. When disabled, the writes are not buffered and the CPU must
wait until the write is complete before starting another write cycle.
PCI Delay Transaction (Disabled)
The mainboard’s chipset has an embedded 32-bit post write buffer
to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.1.
Press <Esc> to return to the Advanced Chipset Setup screen.
BIOS Write Protect (Disabled)
Use this item to enable or disable the BIOS Write Protect.
System BIOS/Video RAM Cacheable (Disabled)
These items allow the video and system to be cached in memory
for faster execution. Leave these items at the default value for
better performance.
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