Philips 32PFL4664/F7 - Page 43

9-3
3. Digital Signal Process Block Diagram
DIGITAL MAIN CBA UNIT
IC3101 (DIGITAL SIGNAL PROCESS)
DIGITAL SIGNAL PROCESS
HDMI-IN1
JK3002
DATA0(+) DATA0(-) DATA1(+) DATA1(-) DATA2(+) DATA2(-) HDMI-DATA HDMI-CLOCK
7 9 4 6 1 3
10 12 16 15
7 9 4 6 1 3
10 12 16 15
JK3001
CLOCK(+) CLOCK(-)
AUDIO DECODER
HDMI I/F
TO VIDEO/AUDIO BLOCK DIAGRAM
VIDEO DECODER
VIDEO SIGNAL
AUDIO SIGNAL
A/D CONVERTER
SW
CVBS-VIDEO-IN
DEMODULATOR /MPEG DECODER
AUDIO I/F
DIF-OUT1 DIF-OUT2 IF-AGC
IF-AGC
I2S-OUT-WS I2S-OUT-BCK
SPDIF
CVBS-AUDIO(L)-IN CVBS-AUDIO(R)-IN
DATA0(+) DATA0(-) DATA1(+) DATA1(-) DATA2(+) DATA2(-) HDMI-DATA HDMI-CLOCK CLOCK(+) CLOCK(-)
K6
J20 J21
R3
P2
R18
D2 D1
E2 E3
F2 F3
D3 C1
E5 E4
W2
W1
U4
LCD PANEL ASSEMBLY
HDMI-IN2
HDMI SW
MEMORY I/F
DATA(0-7)
IC3102
(NAND FLASH MEMORY)
NAND-AD(0-7)
ADDRESS
IC3401
(DDR3 SDRAM)
A(0-14)
G2 G1
H2 H3
J2 J3
G3
F1 F6 F5
LVDS TX
I2S-OUT-MCK
K19
I2S-OUT-SD
J19
DQU(0-7),DQL(0-7)
DATA
CN2001
CN2001
U20
31 30 29 28 27
GCLK1 GCLK2 GCLK3 GCLK4 GCLK5
CN2001
L20
M19
M20
K21 K20
U19
M21
N19
L19
44 43 41 40 38 37 47 46
LVDS2(-) LVDS2(+) LVDS1(-) LVDS1(+) LVDS0(-) LVDS0(+) LCLK(-) LCLK(+)
49 SOESOE
GST
GCLK
MCLK
E/O
55
4
T20
2
T21
3
V19
I2C-SCL
P17
I2C-SDA
P16
5
20 21
54 53 52 51
26 GCLK6
50
LEVEL SHIFTER
CONTROL LOGIC
25 24 20 19
VGH-R VGH-F VST GIP-RESET
49 48 45 44
LEVEL SHIFTER
23 22
VGH-ODD VGH-EVEN
47 46
LEVEL SHIFTER
17 16
VCOM-FB VCOM
39 38
14 GMA12
36
DECODER
I2C INTERFACE
13 12
GMA11 GMA10
35 34
11 GMA5
33
10
9
GMA4 GMA3
32 31
IC2001 (POWER MANAGEMENT)
VCC+3.3V
PL19.00BLD