10-20
8NU
10FRC-RDY
3UART-RX-FRC
1FRC-CTRL2
18GND
45GND
CN5001
51LCD+2.7V
9LCD-PON
50LCD+2.7V
48LCD+2.7V
11PROTECT3
21GND
44GND
0.1
C5023
7FRC-CTL1
2LCD-RESET
49LCD+2.7V
2200P
C5022
5FRC-SCL
47LCD+2.7V
12NU
14LVDS-ED4(+)
13GND
15LVDS-ED4(-)
17LVDS-ED3(-)
16LVDS-ED3(+)
20LVDS-ECLK(-)
19LVDS-ECLK(+)
23LVDS-ED2(-)
22LVDS-ED2(+)
25LVDS-ED1(-)
24LVDS-ED1(+)
26LVDS-ED0(+)
27LVDS-ED0(-)
28GND
30LVDS-OD4(-)
29LVDS-OD4(+)
31LVDS-OD3(+)
32LVDS-OD3(-)
33GND
34LVDS-OCLK(+)
35LVDS-OCLK(-)
36GND
38LVDS-OD2(-)
37LVDS-OD2(+)
40LVDS-OD1(-)
39LVDS-OD1(+)
41LVDS-OD0(+)
42LVDS-OD0(-)
43GND
4.7
C5024
P-ON+3.3V
AF20
IC5001(4/5)
PNX5100EH
*2
LCD+2.7V
0.1C5016
BEADBC5001
0.1C5017
10C5018
0.1C5019
*AGND
100R5007
FRC-CTRL2
OPEN
C5009
OPEN
C5011
LCD-RESET
OPENR5011
4UART-TX-FRC
6FRC-SDA
OPEN
C5012
OPEN
C5014
100R5009
100R5008
FRC-CTRL1
100R5010
OPEN
C5015
100R5301
PROTECT3
46LCD+2.7V
AB15 VDD-3V3-LVDSIN-1
AB17 VDD-3V3-LVDSIN-2
AB18 VDDA-3V3-LVDSIN
AB19 GND
BEADBC5002
UART-TX-FRC
FRC-SDA
FRC-SCL
UART-RX-FRC
LCD-PON
FRC-RDY
G3NU
G2NU
F4NU
G1NU
E3NU
E1NU
F3NU
F2NU
F1NU
D2NU
D1NU
C1NU
A2NU
A3NU
B3NU
B4NU
C4NU
A5NU
B5NU
C5NU
D5NU
A6NU
B6NU
C6NU
A7NU
B7NU
C7NU
D7NU
D8NU
C8NU
A8NU
B8NU
D6NU
A4NU
E2NU
G4NU
10K
R5038
D5001
OPEN
AE19
AC19
AF18
AE20
AE18
AC20
AC18
AD20
AD18
AF19
AD19
AC15
AD15
AE16
AF16
AD16
AF15
AC16
AE17
AC17
AE15
AD17
AF17
3
2
4
1
VUXST W
LVDS
OUTPUT
TO FRC 1
IC5001(1/5)
*A:A1,A10,A13,A17,A20,B1,B2,C2,C3,C25,D3,D4,E4,E5,F25,H23,
J3,J4,J25,K3,K4,L11~L15,M11~M15,M25,N11~N15,P11~P15,P23,
R11~R15,R23,R25,T11~T15,U3,U4,V25,W23,AA25,AB3~AB5,AC1~AC4,
AD1~AD3,AD24,AE1,AE2,AE26,AF1,AB13,AC13
FRC CBA UNIT
CONTINUE
FRC 1
CONTINUE
FRC 5
CONTINUE
FRC 3
CONTINUE
FRC 5
(FRAME RATE CONVERTER)
TO DIGITAL MAIN
CBA UNIT CN3901
PL11.9SCFR4
FRC 4 Schematic Diagram
The order of pins shown in this diagram is different from that of actual IC5001.
IC5001 is divided into five and shown as IC5001 (1/5) ~ IC5001 (5/5) in this FRC Schematic Diagram Section.
2 NOTE:
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