Electrical diagrams and PWB’s
GB 43CDR 3rd gen. 7.
C
D
F980 F9
F981 F9
91011
A
B
3898-D F12
3999 G12
5712 B9
5713 B4
5716 G7
7702 C3
7703 C9
2715 B5
2720 H9
3754 H7
12
C
D
E
F
7705-A G11
7708-A G8
12 13
123
A
B
678
7708-D H7
7999 G12
7708-B G7
7708-C H10
567891011
F754 B4
F755 B10
12 13
I
2700 B5
2701 B5
2702 B5
2705 G7
E
F
G
H
I
F902 H7
F904 H7
F947 E10
F950 H11
F950
2710 B10
2711 B10
G
H
3759 I7
3780 I10
3817 E10
34
45
2711
100n
9
10
7
14
8
F755
7708-C
74HC00D
74HC00D
7708-B
4
5
7
14
6
F902
100n
2700
F904
3759
1K
3754
1K
BLM21
5713
F981
5712
BLM21
31
NC1
11
NC2
12
NC3
32
OE_
29
RAS_
14
UCAS_
30
VCC1
1
VCC2
6
VCC3
21
VSS1
22
VSS2
37
VSS3
42
WE_
13
2
I|O1
3
35
I|O10
I|O11
36
I|O12
38
I|O13
39
I|O14
40
I|O15
41
I|O2
4
I|O3
5
I|O4
7
I|O5
8
I|O6
9
I|O7
10
I|O8
33
I|O9
34
LCAS_
7702
GM71C18163CJ-6
A0
17
A1
18
A10
16
A11
15
A2
19
A3
20
A4
23
A5
24
A6
25
A7
26
A8
27
A9
28
I|O0
100u
2701
2720
1n
3780
100K
11
WE_
35
DQ3
38
DQ4
40
DQ5
42
DQ6
44
DQ7
30
DQ8
32
DQ9
10
NC2
13
NC3
14
NC4
28
OE_
12
RESET_
15
RY|BY_
37
VCC
27
VSS1
46
VSS2
20
A5
19
A6
18
A7
8
A8
7
A9
47
BYTE_
26
CE_
29
DQ0
31
DQ1
34
DQ10
36
DQ11
39
DQ12
41
DQ13
43
DQ14
45
DQ15|A-1
33
DQ2
25
A0
24
A1
6
A10
5
A11
4
A12
3
A13
2
A14
1
A15
48
A16
17
A17
16
A18
9
A19
23
A2
22
A3
21
A4
3817
1K
7703
Am29LV160BB
5716
BLM21
12
13
7
14
11
100n
2702
74HC00D
7708-D
100n
2705
3898-D
47R
2710
F980
100u
2
1
8
4
MAIN-4228-CDR99
PB CDRW
3104 123 4228
0R
3999
7705-A
MC34072
3
BC848B
7999
1
2
7
14
3
F754
7708-A
74HC00D
F947
{RAS0,CAS0,CAS1,DRAW_RW,F_READY,CSFLASH,F_RW,RESET_MIN}
+12VX
V7708
D(16:31)
SYS_CLK_IIW
SYS_CLK_11B
2715
100n
D(31)
F_RW
D3V3
D3V3
F_READY
D3V3
A(19)
A(20)
RESET_MIN
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
V7708
V7708
WRITE_TOGGLE
D3V3
V7708
V7708
D3V3
A(15)
A(16)
A(17)
A(18)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
CSFLASH
A(1:20)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
A(10)
A(20)
D(16)
D(17)
D(26)
D(27)
D(28)
D(29)
D(30)
D(31)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
CAS1
RAS0
CAS0
DRAW_RW
A(1)
A(2)
A(11)
A(12)
A(13)
A(14)
CDR MAIN BOARD - CIRCUIT DIAGRAM 10 : DASP FLASH & DRAM TESTPOINTS
R7
CL06532018_085.eps
010300
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