Philips CDR880 - Signal Conversion and Encoding;Decoding; Analogue to Digital Conversion Process; CIRC EFM Encoding Process; Output Path with Decoder

18
BASICS CDR/RW
The Digital Audio Input/Output circuit (DAIO) calculates a new
digital output signal. So digital Monitoring of the input signal is
possible via this output signal. See figure 26.
Blockdiagram
TDA1315
SST Six
See ly ee
ae EE
sie
EPPA
Figure 26
Blockdiagram of the Digital Audio input/output
3.3.1.2 Analogue Digital converter
The analogue input signal is converted in the Analogue/Digital
converter IC (ADC) into the ?S bus format. In figure 27 the
blockdiagram of this IC is shown. Conversion is done via the
Sigma/Delta modulator. After that the digital data is led to the
CDCEP (Compact Disc CIRC Encoder Plus) via the datapath
bus.
Blockdiagram
REF. VOLTAGE
p GENERATOR CLOCKGENERATOR | GKIN
os & CONTROL
TA DECIMATION FILTER
SMING a | Ta
TER | FILTERS
GENERATOR Cone | ALFANO
Figure 27
Blockdiagram of the conversion from Analogue to the
EFM format
3.3.1.3 Cross Interleave Read/Solomon Code to
Eight-to-Fourteen-Modulation (CIRC EFM) Encoder
In the CDCEP the I2S signal will be converted into the EFM
format. To get this format the data has been shifted into a
RAM memory, split up in symbols and read out via the enco-
der pattern. In the CIRC circuit the error correction symbols
will be added. Also the subcode information from the master
uP will be prepared in the subcode shiftregister and the
subcode bits are also added via CIRC to the EFM format.
Here e.g. the copy bit information has been written to the disc.
After that the conversion from the 8 bit symbols to the 14 bit
has been done and 3 merging bits are added to each 14 bit
pattern. Resulting in the writing EFM-signal. On figure 28 the
blockdiagram of CDCEP encoder is shown.
Blockdiagram
CDCEP 15 14
VCCA —s-VSSA
Fon] a
INTERFACE P QPARITY
(8) GENERATOR
SUBCODE
SBDA | R..WINPUT
INPUT
EFM
TIMING
uCONTROLLER
INTERFACE
Q-CHANNEL PROCESSING
CONTROL aa
WPC TIMING
REG’S
=—
vSS02. VSSD1_ VCCD2 vCCD1
Figure 28
Blockdiagram of the CDCEP encoder
3.3.2 The output part of the circuit with the DECODER path
In the playback mode the reading of the EFM on disc is done.
The HF signal from the disc is decoded in the Decoder IC
CD60. In play back mode the I7S signal from the decoder has
been put through via the Datapath to the DAC IC and further
on to the analogue output stage. On next figure the
blockdiagram of the Decoder IC has been shown.
PHILIPS
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