© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 01 — 15 August 2005 143
Philips Semiconductors
UM10139
Volume 1
Chapter 11: I
2
C interfaces
11.7.1 I
2
C Control Set register (I2CONSET: I2C0, I2C0CONSET - 0xE001 C000
and I2C1, I2C1CONSET - 0xE005
C000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
2
C interface. Writing a one to a bit of this register causes the
corresponding bit in the I
2
C control register to be set. Writing a zero has no effect.
I2EN I
2
C Interface Enable. When I2EN is 1, the I
2
C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
2
C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
2
C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
2
C-bus since, when I2EN is reset, the
I
2
C-bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I
2
C interface to enter master mode and
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
When STA is 1 and the I
2
C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition after
a delay of a half clock period of the internal clock generator. If the I
2
C interface is already
in master mode and data has been transmitted or received, it transmits a repeated START
condition. STA may be set at any time, including when the I
2
C interface is in an addressed
slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is 0,
no START condition or repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
2
C-bus if it the
interface is in master mode, and transmits a START condition thereafter. If the I
2
C
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
Table 136: I
2
C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0xE001 C000
and I2C1, I2C1CONSET - address 0xE005
C000) bit description
Bit Symbol Description Reset
value
1:0 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
2 AA Assert acknowledge flag. See the text below.
3 SI I
2
C interrupt flag. 0
4 STO STOP flag. See the text below. 0
5 STA START flag. See the text below. 0
6 I2EN I
2
C interface enable. See the text below. 0
7 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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