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UM10139
V
olume 1: LPC214x User Manual
Rev
. 01
— 15 August 2005
User manual
Documen
t inf
ormatio
n
Inf
o
Content
Keyw
ords
LPC2141, LPC2142, LPC2144, L
PC2146, LPC214
8, LPC2000, LPC214x,
ARM, ARM7, embedded, 3
2-bit, micr
ocontroller, US
B 2.0, USB de
vice
Abstract
An initial LPC214
x User Manual revision
2
Table of Contents
Main Page
Chapter 1: General Information
3
Introduction
3
Features
3
Applications
4
Device Information
4
Architectural Overview
4
Chapter 25 : Supplementary Information
5
ARM7TDMI-S Processor
5
On-Chip Flash Memory System
6
On-Chip Static RAM (SRAM)
6
Block Diagram
7
Chapter 2: LPC2141/2/4/6/8 Memory Addressing
8
Memory Maps
8
LPC2141/2142/2144/2146/2148 Memory Re-Mapping and Boot Block
11
Memory Map Concepts and Operating Modes 11 Memory Re-Mapping
12
Prefetch Abort and Data Abort Exceptions
15
Chapter 3: System Control Block
16
Summary of System Control Block Functions
16
Pin Description
16
Register Description
17
Crystal Oscillator
18
External Interrupt Inputs
20
Register Description
20
External Interrupt Flag Register (EXTINT - 0Xe01F C140)
21
Interrupt Wakeup Register (INTWAKE - 0Xe01F C144)
22
External Interrupt Mode Register (EXTMODE - 0Xe01F C148)
23
External Interrupt Polarity Register (EXTPOLAR - 0Xe01F C14C)
24
Multiple External Interrupt Pins
25
Other System Controls
26
System Control and Status Flags Register (SCS - 0Xe01F C1A0)
26
Memory Mapping Control
26
Memory Mapping Control Register
26
0Xe01F C040)
26
Memory Mapping Control Usage Notes
27
Phase Locked Loop (PLL)
27
Register Description
28
PLL Control Register (PLL0CON - 0Xe01F C080, PLL1CON - 0Xe01F C0A0)
29
PLL Configuration Register
30
0Xe01F C084, PLL1CFG - 0Xe01F C0A4)
30
PLL Status Register (PLL0STAT - 0Xe01F C088, PLL1STAT - 0Xe01F C0A8)
31
PLL Interrupt
31
PLL Modes
31
PLL Feed Register (PLL0FEED - 0Xe01F C08C, PLL1FEED - 0Xe01F C0AC)
32
PLL and Power-Down Mode
32
PLL Frequency Calculation
33
Procedure for Determining PLL Settings
33
PLL0 and PLL1 Configuring Examples
34
Power Control
35
Register Description
35
Power Control Register (PCON - 0Xe01F COCO)
35
Power Control for Peripherals Register (PCONP - 0Xe01F COC4)
36
Power Control Usage Notes
38
Reset
38
Reset Source Identification Register (RSIR - 0Xe01F C180)
39
VPB Divider
40
Register Description
40
VPBDIV Register (VPBDIV - 0Xe01F C100)
40
Wakeup Timer
41
Brown-Out Detection
42
Code Security Vs. Debugging
43
Chapter 4: Memory Acceleration Module (MAM)
44
Introduction
44
Operation
44
MAM Blocks
45
Flash Memory Bank
45
Instruction Latches and Data Latches
46
Flash Programming Issues
46
MAM Operating Modes
46
MAM Configuration
47
Register Description
47
MAM Control Register
48
MAM Timing Register
48
MAM Usage Notes
49
Chapter 5: Vectored Interrupt Controller (VIC)
50
Features
50
Description
50
Register Description
50
VIC Registers
52
Software Interrupt Register (Vicsoftint - 0Xffff F018)
52
0Xffff F01C)
53
0Xffff F008)
54
Interrupt Enable Register
54
0Xffff F010)
54
Interrupt Enable Clear Register (Vicintenclear - 5.6.2
55
Interrupt Select Register (Vicintselect - 0Xffff F00C)
55
IRQ Status Register (Vicirqstatus -
56
FIQ Status Register (Vicfiqstatus - 0Xffff F004)
57
Vector Control Registers 0-15 (Vicvectcntl0-15 - 0Xffff F200-23C)
57
Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C)
58
Default Vector Address Register (Vicdefvectaddr - 0Xffff F034)
58
Vector Address Register (Vicvectaddr - 0Xffff F030)
58
Protection Enable Register (Vicprotection - 0Xffff F020)
58
Interrupt Sources
59
Spurious Interrupts
61
Details and Case Studies on Spurious Interrupts
61
Workaround
62
Solution 1: Test for an IRQ Received During a Write to Disable Irqs
62
Solution 2: Disable Irqs and Fiqs Using Separate Writes to the CPSR
63
Solution 3: Re-Enable Fiqs at the Beginning of the IRQ Handler
63
VIC Usage Notes
63
Chapter 6 : Pin Configuration
66
LPC2141/2142/2144/2146/2148 Pinout
66
Pin Description for LPC2141/2/4/6/8
68
Chapter 7 : Pin Connect Block
75
Features
75
Applications
75
Description
75
Register Description
75
Pin Function Select Register 0 (PINSEL0 - 0Xe002 C000)
76
Pin Function Select Register 1 (PINSEL1 - 0Xe002 C004)
77
Pin Function Select Register 2 (PINSEL2 - 0Xe002 C014)
79
Pin Function Select Register Values
80
Chapter 8: General Purpose Input/Output Ports (GPIO)
81
Features
81
Applications
81
Pin Description
81
Register Description
81
GPIO Port Direction Register
83
0X3Fff C020
83
Fast GPIO Port Mask Register (FIOMASK, Port 0: FIO0MASK - 0X3Fff C010 and Port 1:FIO1MASK - 0X3Fff C030)
85
GPIO Port Pin Value Register
86
0X3Fff C034)
86
0X3Fff C038)
88
0X3Fff C03C)
90
GPIO Usage Notes
92
Example 1: Sequential Accesses to IOSET and IOCLR Affecting the same GPIO Pin/Bit
92
Example 2: an Immediate Output of 0S and 1S on a GPIO Port
92
Writing to IOSET/IOCLR .Vs. IOPIN
93
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)
95
Features
95
Pin Description
95
Register Description
95
UART0 Receiver Buffer Register (U0RBR - 0Xe000 C000, When DLAB = 0, Read Only)
97
UART0 Transmit Holding Register (U0THR - 0Xe000 C000, When DLAB = 0, Write Only)
97
UART0 Divisor Latch Registers (U0DLL - 0Xe000 C000 and U0DLM - 0Xe000 C004, When 9.3.11 DLAB = 1)
97
UART0 Fractional Divider Register (U0FDR - 0Xe000 C028)
98
UART0 Baudrate Calculation
99
UART0 Interrupt Enable Register (U0IER - 0Xe000 C004, When DLAB = 0)
100
UART0 Interrupt Identification Register (U0IIR - 0Xe000 C008, Read Only)
101
UART0 FIFO Control Register
103
0Xe000 C008)
103
UART0 Line Control Register
103
0Xe000 C00C)
103
UART0 Line Status Register
104
0Xe000 C014, Read Only)
104
UART0 Scratch Pad Register
105
0Xe000 C01C)
105
UART0 Auto-Baud Control Register (U0ACR - 0Xe000 C020)
106
Auto-Baud
106
UART0 Transmit Enable Register (U0TER - 0Xe000 C030)
107
Auto-Baud Modes
108
Architecture
109
Chapter 10 : Universal Asynchronous Receiver/Transmitter 1 (UART1)
112
Features
112
Pin Description
112
Register Description
113
UART1 Transmitter Holding Register (U1THR - 0Xe001 0000, When DLAB = 0 Write Only)
115
UART1 Divisor Latch Registers 0 and 1 (U1DLL - 0Xe001 0000 and U1DLM - 0Xe001 0004, When DLAB = 1)
115
UART1 Fractional Divider Register (U1FDR - 0Xe001 0028)
116
UART1 Baudrate Calculation
117
UART1 Interrupt Enable Register (U1IER - 0Xe001 0004, When DLAB = 0)
118
UART1 Interrupt Identification Register (U1IIR - 0Xe001 0008, Read Only)
119
UART1 FIFO Control Register (U1FCR - 0Xe001 0008)
121
UART1 Line Control Register (U1LCR - 0Xe001 000C)
122
UART1 Modem Control Register (U1MCR - 0Xe001 0010), LPC2144/6/8 Only
123
UART1 Line Status Register (U1LSR - 0Xe001 0014, Read Only)
125
UART1 Modem Status Register (U1MSR - 0Xe001 0018), LPC2144/6/8 Only
127
UART1 Scratch Pad Register (U1SCR - 0Xe001 001C)
127
UART1 Auto-Baud Control Register (U1ACR - 0Xe001 0020)
127
Auto-Baud
128
Auto-Baud Modes
129
UART1 Transmit Enable Register (U1TER - 0Xe001 0030)
130
Architecture
131
Chapter 11: I 2 C Interfaces I 2 C0 and I 2 C1
133
Features
133
Applications
133
Description
133
Pin Description
134
I 2 C Operating Modes
134
Master Transmitter Mode
134
Master Receiver Mode
135
Slave Receiver Mode
136
Slave Transmitter Mode
137
I 2 C Implementation and Operation
138
Input Filters and Output Stages
138
Address Register, I2ADDR
140
Comparator
140
Shift Register, I2DAT
140
Arbitration and Synchronization Logic
140
Serial Clock Generator
141
Timing and Control
141
Control Register, I2CONSET and I2CONCLR
141
Status Decoder and Status Register
142
Register Description
142
C Control Set Register (I2CONSET: I2C0, I2C0CONSET - 0Xe001 C000 and I2C1, I2C1CONSET - 0Xe005 C000)
143
C Control Clear Register (I2CONCLR: I2C0, I2C0CONCLR - 0Xe001 C018 and I2C1, I2C1CONCLR - 0Xe005 C018)
144
(I2STAT: 2 C Status Register
145
I 2 C Data Register
145
I 2 C Slave Address Register
146
I 2 C SCL High Duty Cycle Register
146
I 2 C SCL Low Duty Cycle Register
146
Selecting the Appropriate I C Data Rate and Duty Cycle
146
Details of I C Operating Modes
147
Master Transmitter Mode
148
Master Receiver Mode
148
Slave Receiver Mode
149
Slave Transmitter Mode
153
Miscellaneous States
159
I2STAT = 0Xf8
159
I2STAT = 0X00
159
Some Special Cases
160
Simultaneous Repeated START Conditions from Two Masters
160
Data Transfer after Loss of Arbitration
160
Forced Access to the I C-Bus
160
C-Bus Obstructed by a Low Level on SCL or SDA
161
Bus Error
161
C State Service Routines
162
Initialization
163
C Interrupt Service
163
The State Service Routines
163
Adapting State Services to an Application
163
Software Example
163
Initialization Routine
163
Start Master Transmit Function
163
Start Master Receive Function
164
I 2 C Interrupt Routine
164
Non Mode Specific States
164
State: 0X00
164
Master States
164
State: 0X08
164
State: 0X10
165
Master Transmitter States
165
State: 0X18
165
State: 0X20
165
State: 0X28
165
State: 0X30
166
State: 0X38
166
Master Receive States
166
State: 0X40
166
State: 0X48
166
State: 0X50
167
State: 0X58
167
Slave Receiver States
167
State: 0X60
167
State: 0X68
167
State: 0X70
168
State: 0X78
168
State: 0X80
168
State: 0X88
168
State: 0X90
169
State: 0X98
169
State: 0Xa0
169
Slave Transmitter States
169
State: 0Xa8
169
State: 0Xb0
169
State: 0Xb8
170
State: 0Xc0
170
State: 0Xc8
170
Chapter 12: SPI Interface (SPI0)
171
Features
171
Description
171
SPI Overview
171
SPI Data Transfers
171
General Information
173
Master Operation
173
Slave Operation
174
Exception Conditions
174
Read Overrun
174
Write Collision
174
Mode Fault
175
Slave Abort
175
Pin Description
175
Register Description
175
SPI Control Register
176
SPI Status Register
177
SPI Data Register (S0SPDR - 0Xe002 0008) 178 SPI Clock Counter Register (S0SPCCR - 0Xe002 000C)
178
SPI Interrupt Register
178
Architecture
179
Chapter 13: SSP Controller (SPI1)
180
Features
180
Description
180
Bus Description
181
Texas Instruments Synchronous Serial (SSI) Frame Format
181
SPI Frame Format
182
Clock Polarity (CPOL) and Clock Phase (CPHA) Control
182
SPI Format with CPOL=0,CPHA=0
183
SPI Format with CPOL=0,CPHA=1
184
SPI Format with CPOL = 1,CPHA = 0
185
SPI Format with CPOL = 1,CPHA = 1
186
Semiconductor Microwire Frame Format
186
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
188
Register Description
188
SSP Control Register 0 (SSPCR0 - 0Xe006 8000)
189
SSP Control Register 1 (SSPCR1 - 0Xe006 8004)
190
SSP Data Register (SSPDR - 0Xe006 8008)
191
SSP Status Register (SSPSR - 0Xe006 800C)
191
SSP Clock Prescale Register (SSPCPSR - 0Xe006 8010)
191
SSP Interrupt Mask Set/Clear Register (SSPIMSC - 0Xe006 8014)
192
SSP Raw Interrupt Status Register (SSPRIS - 0Xe006 8018)
192
SSP Masked Interrupt Register (SSPMIS - 0Xe006 801C)
193
SSP Interrupt Clear Register (SSPICR - 0Xe006 8020)
193
Chapter 14: USB Device Controller
194
Introduction
194
Features
195
Fixed Endpoint Configuration
195
Architecture
196
Data Flow
197
Data Flow from USB Host to the Device
197
Data Flow from Device to the Host
197
Slave Mode Transfer
197
DMA Mode Transfer (LPC2146/8 Only)
198
Interfaces
198
Software Interface
198
Register Map
198
USB Device Register Definitions
200
USB Interrupt Status Register (Usbintst - 0Xe01F C1C0)
200
USB Device Interrupt Status Register (Usbdevintst - 0Xe009 0000)
201
USB Device Interrupt Enable Register (Usbdevinten - 0Xe009 0004)
202
USB Device Interrupt Clear Register (Usbdevintclr - 0Xe009 0008)
202
USB Device Interrupt Set Register (Usbdevintset - 0Xe009 000C)
203
USB Device Interrupt Priority Register (Usbdevintpri - 0Xe009 002C)
203
USB Endpoint Interrupt Status Register (Usbepintst - 0Xe009 0030)
204
USB Endpoint Interrupt Enable Register (Usbepinten - 0Xe009 0034)
205
USB Endpoint Interrupt Clear Register (Usbepintclr - 0Xe009 0038)
206
USB Endpoint Interrupt Set Register (Usbepintset - 0Xe009 003C)
207
USB Endpoint Interrupt Priority Register (Usbepintpri - 0Xe009 0040)
207
USB Realize Endpoint Register (Usbreep - 0Xe009 0044)
208
EP_RAM Requirements
209
USB Endpoint Index Register (Usbepin - 0Xe009 0048)
210
USB Maxpacketsize Register (Usbmaxpsize - 0Xe009 004C)
210
USB Receive Data Register (Usbrxdata - 0Xe009 0018)
211
USB Receive Packet Length Register (Usbrxplen - 0Xe009 0020)
211
USB Transmit Data Register (Usbtxdata - 0Xe009 001C)
211
USB Transmit Packet Length Register (Usbtxplen - 0Xe009 0024)
211
USB Control Register (Usbctrl - 0Xe009 0028)
212
Slave Mode Data Transfer
212
USB Command Code Register (Usbcmdcode - 0Xe009 0010)
213
USB Command Data Register (Usbcmddata - 0Xe009 0014)
213
USB DMA Request Status Register (Usbdmarst - 0Xe009 0050)
214
USB DMA Request Clear Register (Usbdmarclr - 0Xe009 0054)
214
USB DMA Request Set Register (Usbdmarset - 0Xe009 0058)
215
USB UDCA Head Register (USBUDCAH - 0Xe009 0080)
216
USB EP DMA Status Register (Usbepdmast - 0Xe009 0084)
217
USB EP DMA Enable Register (Usbepdmaen - 0Xe009 0088)
217
USB EP DMA Disable Register (Usbepdmadis - 0Xe009 008C)
217
USB DMA Interrupt Status Register (Usbdmaintst - 0Xe009 0090)
218
USB DMA Interrupt Enable Register (Usbdmainten - 0Xe009 0094)
218
USB End of Transfer Interrupt Status Register (Usbeotintst - 0Xe009 00A0)
219
USB End of Transfer Interrupt Clear Register (Usbeotintclr - 0Xe009 00A4)
219
USB End of Transfer Interrupt Set Register (Usbeotintset - 0Xe009 00A8)
220
USB New DD Request Interrupt Status Register (Usbnddrintst - 0Xe009 00AC)
220
USB New DD Request Interrupt Clear Register (Usbnddrintclr - 0Xe009 00B0)
220
USB New DD Request Interrupt Set Register (Usbnddrintset - 0Xe009 00B4)
220
USB System Error Interrupt Status Register (Usbsyserrintst - 0Xe009 00B8)
221
USB System Error Interrupt Clear Register (Usbsyserrintclr - 0Xe009 00BC)
221
USB System Error Interrupt Set Register (Usbsyserrintset - 0Xe009 00C0)
221
Protocol Engine Command Description
222
Set Address
223
(Command: 0Xd0, Data: Write 1 Byte)
223
Configure Device (Command: 0Xd8, Data: Write 1 Byte)
223
Set Mode
224
(Command: 0Xf3, Data: Write 1 Byte)
224
Read Current Frame Number (Command: 0Xf5, 14.11 Data: Read 1 or 2 Bytes)
225
Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)
225
Set Device Status (Command: 0Xfe, Data: Write 1 Byte)
225
Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
226
Get Error Code (Command: 0Xff, Data: Read 1 Byte)
226
Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
227
Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
228
Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
229
Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))
229
Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
230
Validate Buffer (Command: 0Xfa, Data: None)
230
DMA Descriptor
230
Next_Dd_Pointer
231
Dma_Mode
232
Next_Dd_Valid
232
Isochronous_Endpoint
232
Max_Packet_Size
232
Dma_Buffer_Length
232
Dma_Buffer_Start_Addr
232
Dd_Retired
232
Dd_Status
232
Packet_Valid
233
Ls_Byte_Extracted
233
Ms_Byte_Extracted
233
Present_Dma_Count
233
Message_Length_Position
233
Isochronous_Packetsize_Memory_Address
233
DMA Operation
234
Triggering the DMA Engine
234
Arbitration between Endpoints
234
Non Isochronous Endpoints - Normal Mode Operation
234
Setting up DMA Transfer
234
Finding DMA Descriptor
234
Transferring the Data
235
Optimizing Descriptor Fetch
235
Ending the Packet Transfer
236
No_Packet DD
236
Concatenated Transfer (ATLE) Mode Operation
236
Setting up the DMA Transfer
239
Finding the DMA Descriptor
239
Transferring the Data
239
Ending the Packet Transfer
239
Isochronous Endpoint Operation
240
Setting up of DMA Transfer
240
Finding the DMA Descriptor
240
Transferring the Data
240
Isochronous out Endpoint Operation Example
241
Chapter 15 : Timer/Counter TIMER0 and TIMER1
242
Features
242
Applications
242
Description
242
Pin Description
242
Register Description
243
Interrupt Register (IR
245
Timer Control Register (TCR, TIMER0: T0TCR - 0Xe000 4004 and TIMER1: T1TCR - 0Xe000 8004)
245
Count Control Register (CTCR, TIMER0: T0CTCR - 0Xe000 4070 and TIMER1: T1TCR - 0Xe000 8070)
246
Timer Counter (TC, TIMER0: T0TC - 0Xe000 4008 and TIMER1: T1TC - 0Xe000 8008)
247
Prescale Register (PR, TIMER0: T0PR - 0Xe000 400C and TIMER1: T1PR - 0Xe000 800C)
247
Prescale Counter Register (PC, TIMER0: T0PC - 0Xe000 4010 and TIMER1: T1PC - 0Xe000 8010)
247
Match Registers (MR0 - MR3)
247
Match Control Register (MCR, TIMER0: T0MCR - 0Xe000 4014 and TIMER1: T1MCR - 0Xe000 8014)
248
Capture Registers (CR0 - CR3)
249
Capture Control Register (CCR, TIMER0: T0CCR - 0Xe000 4028 and TIMER1: T1CCR - 0Xe000 8028)
249
External Match Register (EMR, TIMER0: T0EMR - 0Xe000 403C; and TIMER1: T1EMR - 0Xe000 803C)
250
Example Timer Operation
251
Architecture
252
Chapter 16: Pulse Width Modulator (PWM)
253
Features
253
Description
253
Rules for Single Edge Controlled PWM Outputs
256
Rules for Double Edge Controlled PWM Outputs
257
Pin Description
257
Register Description
257
PWM Interrupt Register (PWMIR - 0Xe001 4000)
259
PWM Timer Control Register (PWMTCR - 0Xe001 4004)
259
PWM Timer Counter
260
PWM Prescale Register (PWMPR - 0Xe001 400C)
260
PWM Prescale Counter Register (PWMPC - 0Xe001 4010)
260
PWM Match Registers
261
PWM Match Control Register (PWMMCR - 0Xe001 4014)
261
PWM Control Register (PWMPCR - 0Xe001 404C)
262
PWM Latch Enable Register (PWMLER - 0Xe001 4050)
263
Chapter 17: Analog-To-Digital Converter (ADC)
265
Features
265
Description
265
Pin Description
265
Register Description
266
A/D Control Register
267
AD1CR - 0Xe006 0000)
267
A/D Global Data Register (AD0GDR - 0Xe003 4004 and AD1GDR - 0Xe006 0004)
268
A/D Global Start Register (ADGSR - 0Xe003 4008)
269
A/D Status Register
269
ADC0: AD0CR - 0Xe003 4004 and ADC1: AD1CR - 0Xe006 0004)
269
A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN - 0Xe003 400C and ADC1: AD1INTEN - 0Xe006 000C)
270
A/D Data Registers
271
0Xe006 0010 to 0Xe006 402C)
271
Operation
272
Hardware-Triggered Conversion
272
Interrupts
272
Accuracy Vs. Digital Receiver
272
Chapter 18 : Digital-To-Analog Converter (DAC)
273
Features
273
Pin Description
273
DAC Register (DACR - 0Xe006 C000)
273
Operation
274
Features
275
Description
275
Architecture
275
Register Description
276
RTC Interrupts
277
Miscellaneous Register Group
277
Interrupt Location Register (ILR - 0Xe002 4000)
277
Clock Tick Counter Register (CTCR - 0Xe002 4004)
278
Clock Control Register (CCR - 0Xe002 4008)
278
Counter Increment Interrupt Register (CIIR - 0Xe002 400C)
278
Alarm Mask Register (AMR - 0Xe002 4010)
279
Consolidated Time Registers
279
Consolidated Time Register 0 (CTIME0 - 0Xe002 4014)
279
Consolidated Time Register 1 (CTIME1 - 0Xe002 4018)
280
Consolidated Time Register 2 (CTIME2 - 0Xe002 401C)
280
Time Counter Group
280
Leap Year Calculation
281
Alarm Register Group
281
RTC Usage Notes
282
Reference Clock Divider (Prescaler)
282
Prescaler Integer Register (PREINT - 0Xe002 4080)
283
Prescaler Fraction Register (PREFRAC - 0Xe002 4084)
283
Example of Prescaler Usage
283
Prescaler Operation
284
RTC External 32 Khz Oscillator Component Selection
285
Chapter 20: Watchdog Timer
287
Features
287
Applications
287
Description
287
Register Description
288
Watchdog Mode Register (WDMOD - 0Xe000 0000)
288
Watchdog Timer Constant Register (WDTC - 0Xe000 0004)
289
Watchdog Feed Register (WDFEED - 0Xe000 0008)
289
Watchdog Timer Value Register (WDTV - 0Xe000 000C)
289
Block Diagram
289
Chapter 21: Flash Memory System and Programming
291
Flash Boot Loader
291
Features
291
Applications
291
Description
291
Memory Map after any Reset
291
Criterion for Valid User Code
292
Communication Protocol
293
ISP Command Format
293
ISP Response Format
293
ISP Data Format
293
ISP Flow Control
293
ISP Command Abort
294
Interrupts During ISP
294
Interrupts During IAP
294
RAM Used by ISP Command Handler
294
RAM Used by IAP Command Handler
294
RAM Used by Realmonitor
294
Boot Process Flowchart
295
Sector Numbers
295
Flash Content Protection Mechanism
296
Code Read Protection (CRP)
297
ISP Commands
297
Unlock <Unlock Code
298
Set Baud Rate <Baud Rate> <Stop Bit
298
Echo <Setting
299
Write to RAM <Start Address> <Number of Bytes
299
Read Memory <Address> <No. of Bytes
300
Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number
300
Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes
301
Go <Address> <Mode
302
Erase Sector(S) <Start Sector Number> <End Sector Number
302
Blank Check Sector(S) <Sector Number> <End Sector Number
303
Read Part Identification Number
303
Read Boot Code Version Number
303
Compare <Address1> <Address2> <No of Bytes
304
ISP Return Codes
304
IAP Commands
305
Prepare Sector(S) for Write Operation
307
Copy RAM to Flash
308
Erase Sector(S)
308
Blank Check Sector(S)
309
Read Part Identification Number
309
Read Boot Code Version Number
309
Compare <Address1> <Address2> <No of Bytes
310
Reinvoke ISP
310
IAP Status Codes
310
JTAG Flash Programming Interface
311
Chapter 22: Embeddedice Logic
312
Features
312
Applications
312
Description
312
Pin Description
313
Reset State of Multiplexed Pins
313
Register Description
314
Block Diagram
314
Chapter 23: Embedded Trace Macrocell (ETM)
315
Features
315
Applications
315
Description
315
ETM Configuration
315
Pin Description
316
Reset State of Multiplexed Pins
316
Register Description
317
Block Diagram
318
Chapter 24: Realmonitor
319
Features
319
Applications
319
Description
319
Realmonitor Components
320
Rmhost
320
Rmtarget
320
How Realmonitor Works
321
How to Enable Realmonitor
322
Adding Stacks
322
IRQ Mode
322
Undef Mode
322
SVC Mode
322
Prefetch Abort Mode
323
Data Abort Mode
323
User/System Mode
323
FIQ Mode
323
Handling Exceptions
323
Realmonitor Exception Handling
323
Rmtarget Initialization
324
Code Example
324
Realmonitor Build Options
327
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Philips LPC214 Series Specifications
General
Brand
Philips
Model
LPC214 Series
Category
Microcontrollers
Language
English
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