Philips LPC214 Series

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User manual Rev. 01 — 15 August 2005 2

Philips Semiconductors

UM10139

Volume 1 LPC2141/2/4/6/8 UM

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For additional information, please visit: http://www.semiconductors.philips.com

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Revision history

Rev Date Description

01 20050815 Initial version

Main Page

Chapter 1: General Information3
Introduction3
Features3
Applications4
Device Information4
Architectural Overview4
Chapter 25 : Supplementary Information5
ARM7TDMI-S Processor5
On-Chip Flash Memory System6
On-Chip Static RAM (SRAM)6
Block Diagram7
Chapter 2: LPC2141/2/4/6/8 Memory Addressing8
Memory Maps8
LPC2141/2142/2144/2146/2148 Memory Re-Mapping and Boot Block11
- Memory Map Concepts and Operating Modes 11 Memory Re-Mapping12
Prefetch Abort and Data Abort Exceptions15
Chapter 3: System Control Block16
Summary of System Control Block Functions16
Pin Description16
Register Description17
Crystal Oscillator18
External Interrupt Inputs20
- Register Description20
- External Interrupt Flag Register (EXTINT - 0Xe01F C140)21
- Interrupt Wakeup Register (INTWAKE - 0Xe01F C144)22
- External Interrupt Mode Register (EXTMODE - 0Xe01F C148)23
- External Interrupt Polarity Register (EXTPOLAR - 0Xe01F C14C)24
- Multiple External Interrupt Pins25
Other System Controls26
- System Control and Status Flags Register (SCS - 0Xe01F C1A0)26
Memory Mapping Control26
- Memory Mapping Control Register26
  - 0Xe01F C040)26
- Memory Mapping Control Usage Notes27
Phase Locked Loop (PLL)27
- Register Description28
- PLL Control Register (PLL0CON - 0Xe01F C080, PLL1CON - 0Xe01F C0A0)29
- PLL Configuration Register30
  - 0Xe01F C084, PLL1CFG - 0Xe01F C0A4)30
- PLL Status Register (PLL0STAT - 0Xe01F C088, PLL1STAT - 0Xe01F C0A8)31
- PLL Interrupt31
- PLL Modes31
- PLL Feed Register (PLL0FEED - 0Xe01F C08C, PLL1FEED - 0Xe01F C0AC)32
- PLL and Power-Down Mode32
- PLL Frequency Calculation33
- Procedure for Determining PLL Settings33
- PLL0 and PLL1 Configuring Examples34
Power Control35
- Register Description35
- Power Control Register (PCON - 0Xe01F COCO)35
- Power Control for Peripherals Register (PCONP - 0Xe01F COC4)36
- Power Control Usage Notes38
Reset38
- Reset Source Identification Register (RSIR - 0Xe01F C180)39
VPB Divider40
- Register Description40
- VPBDIV Register (VPBDIV - 0Xe01F C100)40
Wakeup Timer41
Brown-Out Detection42
Code Security Vs. Debugging43
Chapter 4: Memory Acceleration Module (MAM)44
Introduction44
Operation44
MAM Blocks45
- Flash Memory Bank45
- Instruction Latches and Data Latches46
- Flash Programming Issues46
MAM Operating Modes46
MAM Configuration47
Register Description47
MAM Control Register48
MAM Timing Register48
MAM Usage Notes49
Chapter 5: Vectored Interrupt Controller (VIC)50
Features50
Description50
Register Description50
VIC Registers52
- Software Interrupt Register (Vicsoftint - 0Xffff F018)52
  - 0Xffff F01C)53
  - 0Xffff F008)54
- Interrupt Enable Register54
  - 0Xffff F010)54
- Interrupt Enable Clear Register (Vicintenclear - 5.6.255
- Interrupt Select Register (Vicintselect - 0Xffff F00C)55
- IRQ Status Register (Vicirqstatus -56
- FIQ Status Register (Vicfiqstatus - 0Xffff F004)57
- Vector Control Registers 0-15 (Vicvectcntl0-15 - 0Xffff F200-23C)57
- Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C)58
- Default Vector Address Register (Vicdefvectaddr - 0Xffff F034)58
- Vector Address Register (Vicvectaddr - 0Xffff F030)58
- Protection Enable Register (Vicprotection - 0Xffff F020)58
Interrupt Sources59
Spurious Interrupts61
- Details and Case Studies on Spurious Interrupts61
- Workaround62
- Solution 1: Test for an IRQ Received During a Write to Disable Irqs62
- Solution 2: Disable Irqs and Fiqs Using Separate Writes to the CPSR63
- Solution 3: Re-Enable Fiqs at the Beginning of the IRQ Handler63
VIC Usage Notes63
Chapter 6 : Pin Configuration66
LPC2141/2142/2144/2146/2148 Pinout66
Pin Description for LPC2141/2/4/6/868
Chapter 7 : Pin Connect Block75
Features75
Applications75
Description75
Register Description75
- Pin Function Select Register 0 (PINSEL0 - 0Xe002 C000)76
- Pin Function Select Register 1 (PINSEL1 - 0Xe002 C004)77
- Pin Function Select Register 2 (PINSEL2 - 0Xe002 C014)79
- Pin Function Select Register Values80
Chapter 8: General Purpose Input/Output Ports (GPIO)81
Features81
Applications81
Pin Description81
Register Description81
- GPIO Port Direction Register83
  - 0X3Fff C02083
- Fast GPIO Port Mask Register (FIOMASK, Port 0: FIO0MASK - 0X3Fff C010 and Port 1:FIO1MASK - 0X3Fff C030)85
- GPIO Port Pin Value Register86
GPIO Usage Notes92
- Example 1: Sequential Accesses to IOSET and IOCLR Affecting the same GPIO Pin/Bit92
  - Example 2: an Immediate Output of 0S and 1S on a GPIO Port92
- Writing to IOSET/IOCLR .Vs. IOPIN93
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)95
Features95
Pin Description95
Register Description95
- UART0 Receiver Buffer Register (U0RBR - 0Xe000 C000, When DLAB = 0, Read Only)97
- UART0 Transmit Holding Register (U0THR - 0Xe000 C000, When DLAB = 0, Write Only)97
- UART0 Divisor Latch Registers (U0DLL - 0Xe000 C000 and U0DLM - 0Xe000 C004, When 9.3.11 DLAB = 1)97
- UART0 Fractional Divider Register (U0FDR - 0Xe000 C028)98
- UART0 Baudrate Calculation99
- UART0 Interrupt Enable Register (U0IER - 0Xe000 C004, When DLAB = 0)100
- UART0 Interrupt Identification Register (U0IIR - 0Xe000 C008, Read Only)101
- UART0 FIFO Control Register103
  - 0Xe000 C008)103
- UART0 Line Control Register103
  - 0Xe000 C00C)103
- UART0 Line Status Register104
- UART0 Auto-Baud Control Register (U0ACR - 0Xe000 C020)106
- Auto-Baud106
- UART0 Transmit Enable Register (U0TER - 0Xe000 C030)107
- Auto-Baud Modes108
Architecture109
Chapter 10 : Universal Asynchronous Receiver/Transmitter 1 (UART1)112
Features112
Pin Description112
Register Description113
- UART1 Transmitter Holding Register (U1THR - 0Xe001 0000, When DLAB = 0 Write Only)115
- UART1 Divisor Latch Registers 0 and 1 (U1DLL - 0Xe001 0000 and U1DLM - 0Xe001 0004, When DLAB = 1)115
- UART1 Fractional Divider Register (U1FDR - 0Xe001 0028)116
- UART1 Baudrate Calculation117
- UART1 Interrupt Enable Register (U1IER - 0Xe001 0004, When DLAB = 0)118
- UART1 Interrupt Identification Register (U1IIR - 0Xe001 0008, Read Only)119
- UART1 FIFO Control Register (U1FCR - 0Xe001 0008)121
- UART1 Line Control Register (U1LCR - 0Xe001 000C)122
- UART1 Modem Control Register (U1MCR - 0Xe001 0010), LPC2144/6/8 Only123
- UART1 Line Status Register (U1LSR - 0Xe001 0014, Read Only)125
- UART1 Modem Status Register (U1MSR - 0Xe001 0018), LPC2144/6/8 Only127
- UART1 Scratch Pad Register (U1SCR - 0Xe001 001C)127
- UART1 Auto-Baud Control Register (U1ACR - 0Xe001 0020)127
- Auto-Baud128
- Auto-Baud Modes129
- UART1 Transmit Enable Register (U1TER - 0Xe001 0030)130
Architecture131
Chapter 11: I 2 C Interfaces I 2 C0 and I 2 C1133
Features133
Applications133
Description133
Pin Description134
I 2 C Operating Modes134
- Master Transmitter Mode134
- Master Receiver Mode135
- Slave Receiver Mode136
- Slave Transmitter Mode137
I 2 C Implementation and Operation138
- Input Filters and Output Stages138
- Address Register, I2ADDR140
- Comparator140
- Shift Register, I2DAT140
- Arbitration and Synchronization Logic140
- Serial Clock Generator141
- Timing and Control141
- Control Register, I2CONSET and I2CONCLR141
- Status Decoder and Status Register142
Register Description142
- C Control Set Register (I2CONSET: I2C0, I2C0CONSET - 0Xe001 C000 and I2C1, I2C1CONSET - 0Xe005 C000)143
- C Control Clear Register (I2CONCLR: I2C0, I2C0CONCLR - 0Xe001 C018 and I2C1, I2C1CONCLR - 0Xe005 C018)144
- (I2STAT: 2 C Status Register145
- I 2 C Data Register145
- I 2 C Slave Address Register146
- I 2 C SCL High Duty Cycle Register146
- I 2 C SCL Low Duty Cycle Register146
- Selecting the Appropriate I C Data Rate and Duty Cycle146
Details of I C Operating Modes147
- Master Transmitter Mode148
- Master Receiver Mode148
- Slave Receiver Mode149
- Slave Transmitter Mode153
- Miscellaneous States159
- I2STAT = 0Xf8159
- I2STAT = 0X00159
- Some Special Cases160
- Simultaneous Repeated START Conditions from Two Masters160
- Data Transfer after Loss of Arbitration160
- Forced Access to the I C-Bus160
- C-Bus Obstructed by a Low Level on SCL or SDA161
- Bus Error161
  - C State Service Routines162
- Initialization163
- C Interrupt Service163
  - The State Service Routines163
- Adapting State Services to an Application163
Software Example163
- Initialization Routine163
- Start Master Transmit Function163
- Start Master Receive Function164
- I 2 C Interrupt Routine164
- Non Mode Specific States164
- State: 0X00164
- Master States164
- State: 0X08164
- State: 0X10165
- Master Transmitter States165
- State: 0X18165
- State: 0X20165
- State: 0X28165
- State: 0X30166
- State: 0X38166
- Master Receive States166
- State: 0X40166
- State: 0X48166
- State: 0X50167
- State: 0X58167
- Slave Receiver States167
- State: 0X60167
- State: 0X68167
- State: 0X70168
- State: 0X78168
- State: 0X80168
- State: 0X88168
- State: 0X90169
- State: 0X98169
- State: 0Xa0169
- Slave Transmitter States169
- State: 0Xa8169
- State: 0Xb0169
- State: 0Xb8170
- State: 0Xc0170
- State: 0Xc8170
Chapter 12: SPI Interface (SPI0)171
Features171
Description171
- SPI Overview171
- SPI Data Transfers171
- General Information173
- Master Operation173
- Slave Operation174
- Exception Conditions174
- Read Overrun174
- Write Collision174
- Mode Fault175
- Slave Abort175
Pin Description175
Register Description175
- SPI Control Register176
- SPI Status Register177
- SPI Data Register (S0SPDR - 0Xe002 0008) 178 SPI Clock Counter Register (S0SPCCR - 0Xe002 000C)178
- SPI Interrupt Register178
Architecture179
Chapter 13: SSP Controller (SPI1)180
Features180
Description180
Bus Description181
- Texas Instruments Synchronous Serial (SSI) Frame Format181
- SPI Frame Format182
- Clock Polarity (CPOL) and Clock Phase (CPHA) Control182
- SPI Format with CPOL=0,CPHA=0183
- SPI Format with CPOL=0,CPHA=1184
- SPI Format with CPOL = 1,CPHA = 0185
- SPI Format with CPOL = 1,CPHA = 1186
- Semiconductor Microwire Frame Format186
- Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode188
Register Description188
- SSP Control Register 0 (SSPCR0 - 0Xe006 8000)189
- SSP Control Register 1 (SSPCR1 - 0Xe006 8004)190
- SSP Data Register (SSPDR - 0Xe006 8008)191
- SSP Status Register (SSPSR - 0Xe006 800C)191
- SSP Clock Prescale Register (SSPCPSR - 0Xe006 8010)191
- SSP Interrupt Mask Set/Clear Register (SSPIMSC - 0Xe006 8014)192
- SSP Raw Interrupt Status Register (SSPRIS - 0Xe006 8018)192
- SSP Masked Interrupt Register (SSPMIS - 0Xe006 801C)193
- SSP Interrupt Clear Register (SSPICR - 0Xe006 8020)193
Chapter 14: USB Device Controller194
Introduction194
Features195
Fixed Endpoint Configuration195
Architecture196
Data Flow197
- Data Flow from USB Host to the Device197
- Data Flow from Device to the Host197
- Slave Mode Transfer197
- DMA Mode Transfer (LPC2146/8 Only)198
Interfaces198
- Software Interface198
- Register Map198
USB Device Register Definitions200
- USB Interrupt Status Register (Usbintst - 0Xe01F C1C0)200
- USB Device Interrupt Status Register (Usbdevintst - 0Xe009 0000)201
- USB Device Interrupt Enable Register (Usbdevinten - 0Xe009 0004)202
- USB Device Interrupt Clear Register (Usbdevintclr - 0Xe009 0008)202
- USB Device Interrupt Set Register (Usbdevintset - 0Xe009 000C)203
- USB Device Interrupt Priority Register (Usbdevintpri - 0Xe009 002C)203
- USB Endpoint Interrupt Status Register (Usbepintst - 0Xe009 0030)204
- USB Endpoint Interrupt Enable Register (Usbepinten - 0Xe009 0034)205
- USB Endpoint Interrupt Clear Register (Usbepintclr - 0Xe009 0038)206
- USB Endpoint Interrupt Set Register (Usbepintset - 0Xe009 003C)207
- USB Endpoint Interrupt Priority Register (Usbepintpri - 0Xe009 0040)207
- USB Realize Endpoint Register (Usbreep - 0Xe009 0044)208
EP_RAM Requirements209
- USB Endpoint Index Register (Usbepin - 0Xe009 0048)210
- USB Maxpacketsize Register (Usbmaxpsize - 0Xe009 004C)210
- USB Receive Data Register (Usbrxdata - 0Xe009 0018)211
- USB Receive Packet Length Register (Usbrxplen - 0Xe009 0020)211
- USB Transmit Data Register (Usbtxdata - 0Xe009 001C)211
- USB Transmit Packet Length Register (Usbtxplen - 0Xe009 0024)211
- USB Control Register (Usbctrl - 0Xe009 0028)212
- Slave Mode Data Transfer212
- USB Command Code Register (Usbcmdcode - 0Xe009 0010)213
- USB Command Data Register (Usbcmddata - 0Xe009 0014)213
- USB DMA Request Status Register (Usbdmarst - 0Xe009 0050)214
- USB DMA Request Clear Register (Usbdmarclr - 0Xe009 0054)214
- USB DMA Request Set Register (Usbdmarset - 0Xe009 0058)215
- USB UDCA Head Register (USBUDCAH - 0Xe009 0080)216
- USB EP DMA Status Register (Usbepdmast - 0Xe009 0084)217
- USB EP DMA Enable Register (Usbepdmaen - 0Xe009 0088)217
- USB EP DMA Disable Register (Usbepdmadis - 0Xe009 008C)217
- USB DMA Interrupt Status Register (Usbdmaintst - 0Xe009 0090)218
- USB DMA Interrupt Enable Register (Usbdmainten - 0Xe009 0094)218
- USB End of Transfer Interrupt Status Register (Usbeotintst - 0Xe009 00A0)219
- USB End of Transfer Interrupt Clear Register (Usbeotintclr - 0Xe009 00A4)219
- USB End of Transfer Interrupt Set Register (Usbeotintset - 0Xe009 00A8)220
- USB New DD Request Interrupt Status Register (Usbnddrintst - 0Xe009 00AC)220
- USB New DD Request Interrupt Clear Register (Usbnddrintclr - 0Xe009 00B0)220
- USB New DD Request Interrupt Set Register (Usbnddrintset - 0Xe009 00B4)220
- USB System Error Interrupt Status Register (Usbsyserrintst - 0Xe009 00B8)221
- USB System Error Interrupt Clear Register (Usbsyserrintclr - 0Xe009 00BC)221
- USB System Error Interrupt Set Register (Usbsyserrintset - 0Xe009 00C0)221
Protocol Engine Command Description222
- Set Address223
  - (Command: 0Xd0, Data: Write 1 Byte)223
- Configure Device (Command: 0Xd8, Data: Write 1 Byte)223
- Set Mode224
  - (Command: 0Xf3, Data: Write 1 Byte)224
Read Current Frame Number (Command: 0Xf5, 14.11 Data: Read 1 or 2 Bytes)225
- Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)225
- Set Device Status (Command: 0Xfe, Data: Write 1 Byte)225
- Get Device Status (Command: 0Xfe, Data: Read 1 Byte)226
- Get Error Code (Command: 0Xff, Data: Read 1 Byte)226
- Read Error Status (Command: 0Xfb, Data: Read 1 Byte)227
- Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))228
- Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)229
- Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))229
- Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))230
- Validate Buffer (Command: 0Xfa, Data: None)230
DMA Descriptor230
- Next_Dd_Pointer231
- Dma_Mode232
- Next_Dd_Valid232
- Isochronous_Endpoint232
- Max_Packet_Size232
- Dma_Buffer_Length232
- Dma_Buffer_Start_Addr232
- Dd_Retired232
- Dd_Status232
- Packet_Valid233
- Ls_Byte_Extracted233
- Ms_Byte_Extracted233
- Present_Dma_Count233
- Message_Length_Position233
- Isochronous_Packetsize_Memory_Address233
DMA Operation234
- Triggering the DMA Engine234
- Arbitration between Endpoints234
Non Isochronous Endpoints - Normal Mode Operation234
- Setting up DMA Transfer234
- Finding DMA Descriptor234
- Transferring the Data235
- Optimizing Descriptor Fetch235
- Ending the Packet Transfer236
- No_Packet DD236
Concatenated Transfer (ATLE) Mode Operation236
- Setting up the DMA Transfer239
- Finding the DMA Descriptor239
- Transferring the Data239
- Ending the Packet Transfer239
Isochronous Endpoint Operation240
- Setting up of DMA Transfer240
- Finding the DMA Descriptor240
- Transferring the Data240
- Isochronous out Endpoint Operation Example241
Chapter 15 : Timer/Counter TIMER0 and TIMER1242
Features242
Applications242
Description242
Pin Description242
Register Description243
- Interrupt Register (IR245
- Timer Control Register (TCR, TIMER0: T0TCR - 0Xe000 4004 and TIMER1: T1TCR - 0Xe000 8004)245
- Count Control Register (CTCR, TIMER0: T0CTCR - 0Xe000 4070 and TIMER1: T1TCR - 0Xe000 8070)246
- Timer Counter (TC, TIMER0: T0TC - 0Xe000 4008 and TIMER1: T1TC - 0Xe000 8008)247
- Prescale Register (PR, TIMER0: T0PR - 0Xe000 400C and TIMER1: T1PR - 0Xe000 800C)247
- Prescale Counter Register (PC, TIMER0: T0PC - 0Xe000 4010 and TIMER1: T1PC - 0Xe000 8010)247
- Match Registers (MR0 - MR3)247
- Match Control Register (MCR, TIMER0: T0MCR - 0Xe000 4014 and TIMER1: T1MCR - 0Xe000 8014)248
- Capture Registers (CR0 - CR3)249
- Capture Control Register (CCR, TIMER0: T0CCR - 0Xe000 4028 and TIMER1: T1CCR - 0Xe000 8028)249
- External Match Register (EMR, TIMER0: T0EMR - 0Xe000 403C; and TIMER1: T1EMR - 0Xe000 803C)250
Example Timer Operation251
Architecture252
Chapter 16: Pulse Width Modulator (PWM)253
Features253
Description253
- Rules for Single Edge Controlled PWM Outputs256
- Rules for Double Edge Controlled PWM Outputs257
Pin Description257
Register Description257
- PWM Interrupt Register (PWMIR - 0Xe001 4000)259
- PWM Timer Control Register (PWMTCR - 0Xe001 4004)259
- PWM Timer Counter260
- PWM Prescale Register (PWMPR - 0Xe001 400C)260
- PWM Prescale Counter Register (PWMPC - 0Xe001 4010)260
- PWM Match Registers261
- PWM Match Control Register (PWMMCR - 0Xe001 4014)261
- PWM Control Register (PWMPCR - 0Xe001 404C)262
- PWM Latch Enable Register (PWMLER - 0Xe001 4050)263
Chapter 17: Analog-To-Digital Converter (ADC)265
Features265
Description265
Pin Description265
Register Description266
- A/D Control Register267
  - AD1CR - 0Xe006 0000)267
- A/D Global Data Register (AD0GDR - 0Xe003 4004 and AD1GDR - 0Xe006 0004)268
- A/D Global Start Register (ADGSR - 0Xe003 4008)269
- A/D Status Register269
  - ADC0: AD0CR - 0Xe003 4004 and ADC1: AD1CR - 0Xe006 0004)269
- A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN - 0Xe003 400C and ADC1: AD1INTEN - 0Xe006 000C)270
- A/D Data Registers271
  - 0Xe006 0010 to 0Xe006 402C)271
Operation272
- Hardware-Triggered Conversion272
- Interrupts272
  - Accuracy Vs. Digital Receiver272
Chapter 18 : Digital-To-Analog Converter (DAC)273
Features273
Pin Description273
DAC Register (DACR - 0Xe006 C000)273
Operation274
Features275
Description275
Architecture275
Register Description276
- RTC Interrupts277
- Miscellaneous Register Group277
- Interrupt Location Register (ILR - 0Xe002 4000)277
- Clock Tick Counter Register (CTCR - 0Xe002 4004)278
- Clock Control Register (CCR - 0Xe002 4008)278
- Counter Increment Interrupt Register (CIIR - 0Xe002 400C)278
- Alarm Mask Register (AMR - 0Xe002 4010)279
- Consolidated Time Registers279
- Consolidated Time Register 0 (CTIME0 - 0Xe002 4014)279
- Consolidated Time Register 1 (CTIME1 - 0Xe002 4018)280
- Consolidated Time Register 2 (CTIME2 - 0Xe002 401C)280
- Time Counter Group280
- Leap Year Calculation281
- Alarm Register Group281
RTC Usage Notes282
Reference Clock Divider (Prescaler)282
- Prescaler Integer Register (PREINT - 0Xe002 4080)283
- Prescaler Fraction Register (PREFRAC - 0Xe002 4084)283
- Example of Prescaler Usage283
- Prescaler Operation284
RTC External 32 Khz Oscillator Component Selection285
Chapter 20: Watchdog Timer287
Features287
Applications287
Description287
Register Description288
- Watchdog Mode Register (WDMOD - 0Xe000 0000)288
- Watchdog Timer Constant Register (WDTC - 0Xe000 0004)289
- Watchdog Feed Register (WDFEED - 0Xe000 0008)289
- Watchdog Timer Value Register (WDTV - 0Xe000 000C)289
Block Diagram289
Chapter 21: Flash Memory System and Programming291
Flash Boot Loader291
Features291
Applications291
Description291
- Memory Map after any Reset291
- Criterion for Valid User Code292
- Communication Protocol293
- ISP Command Format293
- ISP Response Format293
- ISP Data Format293
- ISP Flow Control293
- ISP Command Abort294
- Interrupts During ISP294
- Interrupts During IAP294
- RAM Used by ISP Command Handler294
- RAM Used by IAP Command Handler294
- RAM Used by Realmonitor294
- Boot Process Flowchart295
Sector Numbers295
Flash Content Protection Mechanism296
Code Read Protection (CRP)297
ISP Commands297
- Unlock <Unlock Code298
- Set Baud Rate <Baud Rate> <Stop Bit298
- Echo <Setting299
- Write to RAM <Start Address> <Number of Bytes299
- Read Memory <Address> <No. of Bytes300
- Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number300
- Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes301
- Go <Address> <Mode302
- Erase Sector(S) <Start Sector Number> <End Sector Number302
- Blank Check Sector(S) <Sector Number> <End Sector Number303
- Read Part Identification Number303
- Read Boot Code Version Number303
- Compare <Address1> <Address2> <No of Bytes304
- ISP Return Codes304
IAP Commands305
- Prepare Sector(S) for Write Operation307
- Copy RAM to Flash308
- Erase Sector(S)308
- Blank Check Sector(S)309
- Read Part Identification Number309
- Read Boot Code Version Number309
- Compare <Address1> <Address2> <No of Bytes310
- Reinvoke ISP310
- IAP Status Codes310
JTAG Flash Programming Interface311
Chapter 22: Embeddedice Logic312
Features312
Applications312
Description312
Pin Description313
Reset State of Multiplexed Pins313
Register Description314
Block Diagram314
Chapter 23: Embedded Trace Macrocell (ETM)315
Features315
Applications315
Description315
- ETM Configuration315
Pin Description316
Reset State of Multiplexed Pins316
Register Description317
Block Diagram318
Chapter 24: Realmonitor319
Features319
Applications319
Description319
- Realmonitor Components320
- Rmhost320
- Rmtarget320
- How Realmonitor Works321
How to Enable Realmonitor322
- Adding Stacks322
- IRQ Mode322
- Undef Mode322
- SVC Mode322
- Prefetch Abort Mode323
- Data Abort Mode323
- User/System Mode323
- FIQ Mode323
- Handling Exceptions323
- Realmonitor Exception Handling323
- Rmtarget Initialization324
- Code Example324
Realmonitor Build Options327

Philips LPC214 Series - Page 2

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