Philips S42SD-YD09 - Block Diagrams, Test Point Overview, and Waveforms; Block Diagram for Logic Circuit

Block Diagrams, Test Point Overview, and Waveforms
EN 57SDI PDP 2K6 6.
6.2 Block Diagram for Logic Circuit
Figure 6-3 Block diagram (42" SD v5)
Figure 6-4 Block diagram (42" HD w1)
Figure 6-5 Block diagram (50" HD w1 and 63” HD v4)
ASIC
SPS-S101
128K
DDR
128K
DDR
LVD S
IN PUT
(CLOCK
R,G,B Data
V, H Sync.
DE)
I2 C
In terfa c e
Sig nal
X, Y
FET
Co ntrol
TC P
CL K, D ATA
Co ntrol
Logic Main Block Diagram
ASIC
SPS-S101
128 M
DDR
128M
DDR
LVD S
IN PUT
(CLOCK
R,G,B Data
V, H Sync.
DE)
I2 C
In terfa c e
Sig nal
X, Y
FET
Co ntrol
TC P
CL K, D ATA
Co ntrol
Logic Main Block Diagram
G_16380_222.eps
190606
FET
Logic Main Block Diagram
SPS-H102
Interface
Signal
UART
LVDS
ASIC
Input
(Clock
RGB data
V-H-sync.
DE)
X-Y
DDR
128M
DDR
128M
CLK, DATA
TCP
Control
Control
G_16380_223.eps
190606
FET
Logic Main Block Diagram
SPS-H102
Interface
Signal
I2C
LVDS
ASIC
Input
(Clock
RGB data
V-H-sync.
DE)
X-Y
DDR
128M
DDR
128M
CLK, DATA
TCP
Control
Control
G_16380_224.eps
190606