Quantum Q250 User Manual

SECTION 4. APPLICATIONS
4.1
Special Considerations
The following descriptions detail strategies for optimizing data
transfer from Q200 Series drives to host systems.
4.1.1
-REQ/-ACK Handshake
To achieve an optimal transfer rate, the host must assert SCSI signal
-ACK as soon as the data is latched. At the Q250/Q280 target, -ACK
should be received within about 100 ns of the time that the target has
asserted -REQ. If the host waits to assert -ACK until the host has
completed its DMA cycle, the data transmission rate may be signifi-
cantly impaired.
Figure 4-1 illustrates the -REQ/-ACK handshake for a situation where
the Q250/Q280 is the target and is transferring data to the host (the
initiator). The target (Q250/Q280) performs an internal DMA cycle to
bring data from buffer RAM to the SCSI bus; when the data is stable,
the target asserts -REQ. When the initiator detectes -REQ asserted,
it latches the SCSI data and begins its own DMA cycle to transfer the
SCSI data to its internal memory. Two handshake sequences are now
possible.
The sequence for fastest data transfer on the SCSI bus is marked
"Host latches -ACKi 1.25 MByte/sec Transfer Rate." Here the initiator
asserts -ACK as soon as the data is latched, and begins its DMA cycle.
When the target (Q250/Q280) observes -ACK asserted, it deasserts -REQ
to inform the initiator that the data is no longer valid, and immedi-
ately begins a new DMA cycle. The initiator and target DMA cycles
overlap, and a new SCSI cycle begins quickly.
The sequence marked "Host Delays -ACK; 625 KByte/sec Transfer Rate"
results in slower data transfer. Here the initiator does not assert
-ACK until its own DMA cycle is complete. The target does not know
if the initiator has received the data, and must wait for the ini-
tiator to assert -ACK, keeping the data valid during this time. When
the initiator completes its DMA cycle and asserts -ACK, the target
deasserts -REQ to inform the initiator that the data is no longer
valid, and begins a new DMA cycle. The initiator and target DMA
cycles are serial in time.
When the host delays asserting -ACK, the reduction in data transfer
rate is greater than adding the DMA cycle times. DICEY is a state
machine with 400 ns cycle times, servicing the SCSI bus on alternate
cycles. If the target (Q250/Q280) does not observe the assertion of
-ACK within the current SCSI cycle, the Q250/Q280 waits for the next
SCSI cycle, and the data transfer may take twice as long.
4-1

Quantum Q250 Specifications

General

Brand	Quantum
Model	Q250
Category	Storage
Language	English