Symbol
HOLD
(Input)
2/
Function
HOLD
indicates that another master
is requesting the
use
of the
address
and data buses. The cpu,
upon receiving
the
hold
request,
will
relinquish the use of the bus as
soon as the
completion
of the
current
bus transfer. Internal processing
can
continue.
The
processor can regain the bus only after
the
HOLD
is removed.
When
the
HOLD is
acknowledged, the
Address,
Data,
RD, WR,
and
IO/M lines
are 3-stated.
HLDA
(Output)
HOLD
ACKNOWLEDGE:
Indicates that the cpu
has
received
the
HOLD request and that
it
will relinquish
the
bus
in the
next clock cycle.
HLDA goes low after the
Hold request
is re-
moved.
The
cpu
takes the bus
one
half clock
cycle
after
HLDA
goes low.
INTR
(Input)
4
INTERRUPT REQUEST: is used
as
a
general purpose
interrupt.
It is sampled only during the next to the last
clock cycle
of
an
instruction and during
Hold and
Halt states.
If it
is active,
the
Program Counter (PC) will be inhibited from
incrementing
and
an INTA will be issued. During this cycle a
RESTART
or
CALL
instruction can
be
inserted
to
jump
to
the interrupt
service
routine. The
INTR is
enabled and disabled
by software.
It is
disabled
by
Reset and immediately after an interrupt
is accepted.
INTA
(Output)
INTERRUPT ACKNOWLEDGE:
is
used
instead of
(and
has
the same timing
as)
RD
during the Instruction
cycle
after
an
INTR is
accepted.
RST
5.5
RST 6.5
RST
7.5
(Inputs)
RESTART
INTERRUPTS:
These three inputs have
the
same
timing
as INTR except they cause an internal
RESTART
to
be automatically
inserted.
The
priority of these interrupts is
ordered as shown
in
Table
1
.
These interrupts have a higher priority than INTR.
In
addition,
they
may be individually
masked out using
the
SIM instruction.
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