3Z
Symbol
TRAP
(Input)
Function
Trap
interrupt
is a
nonmaskable RESTART interrupt. It
is re-
cognized at the
same
time as 1NTR
or RST
5.5—7.5.
It
is
unaffected
by
any
mask or
Interrupt Enable.
It has the
highest
priority
of any
interrupt. (See Table
1.)
RESET IN
(Input)
Sets the Program
Counter to
zero
and
resets the Interrupt
Enable
and HLDA
flip-flops. The data and
address buses and
the control
lines are 3-stated during
RESET and
because
of
the asynchronous
nature
of RESET, the processor's
internal registers and
flags
may be
altered
by RESET with
unpredictable results. RESET
IN
is
a Schmitt-triggered input, allowing connection to an R-C
network for power-on RESET delay.
The
cpu
is held.
in
the reset
condition
as
long
as
RESET
IN is
applied.
RESET
OUT
(Output)
Indicates
cpu
is being
reset.
Can be used as
a
system reset. The*
signal is
synchronized
to
the
processor
clock and lasts an integral
number of clock
periods.
Xi
,
Xj
(Input)
Xi
and Xj
are
connected to a
crystal,
LC,
or RC network
to
drive the internal
clock generator.
Xi
can also be
an
external
clock input from
a logic gate.
The input frequency is divided
by
2
to
give
the processor's internal operating
frequency.
CLK
(Output)
Clock Output for
use as a system
clock.
The
period of CLK is
twice the
Xi
, X
2
input period.
SID
(Input)
Serial input data line. The
data
on this line
is loaded
into
ac-
cumulator bit 7 whenever a RIM
instruction is
executed.
SOD
(Output)
Serial
output
data line. The output SOD
is set or
reset as specified
by
the SIM instruction.
Vcc
+5
volt supply.
Vss
Ground Reference.
To Next Page
Loading...
