93
Nam*
TRAP
RST
7,5
RST
8.5
RST
5.5
INTR
Priority
Addreis
Branched
To
(1)
Whan
Interrupt
Occurs
24H
3CH
34H
2CH
Typa
Trigger
Rising
edge
AND
high
level
until
sampled.
Rising
edge
patched).
High
level
until
sampled.
See
Note
(2).
High
level
until
sampled.
High
level
until
sampled.
Table
1.
INTERRUPT
PRIORITY,
RESTART
ADDRESS
and
SENSITIVITY
(b) FUNCTIONAL
DESCRIPTION
The
80C85
has twelve
addressable 8-bit registers. Four of
them can
function only
as two
16-bit register pairs.
Six others can be used interchangeably as
8-bit
registers or
as
16-bit
register pairs. The
80C85
register set
is as
follows:
Mnemonic
Register Contents
ACC
or A Accumulator
8
bits
PC
Program Counter 1 6-bit
address
BC, DE, HL General-Purpose
8 bits
x
6
or
Registers: data 1
6
bits x 3
pointer
(HL)
SP
Stack
Pointer
1
6-bit address
Flags
or
F
Flag
Register
5
flags
(8-bit space)
The
80C85
uses a
multiplexed
Data
Bus. The address is split
between
the
higher
8-bit
Address
Bus and
the lower
8-bit Address/Data
Bus. During the
first
T state
(clock cycle)
of
a
machine cycle the
low order address is sent out on
the
Address/Data
bus.
These
lower
8
bits may be latched externally
by
the Address
Latch Enable
signal
(ALE). During
the
rest of the machine
cycle the
data
bus
is
used for memory or I/O data.
The
80C85
provides
RD, WR,
So,
Si
,
and IO/M
signals for bus
control.
An
Interrupt
Acknowledge signal
(INTA)
is also
provided. HOLD,
READY,
and all
Interrupts
are
synchronized with
the processor's internal clock. The
80C85
also
provides
Serial
Input
Data (SID) and Serial Output
Data
(SOD)
lines for
simple serial
interface.
In
addition
to these
features, the
80C85
has
three maskable, vector
interrupt
pins and
one
nonmaskable TRAP interrupt.
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