Radio Shack 26-3801 - Page 38

w
(c)
INTERRUPT
AND SERIAL
I/O
The
80C85
has
5
interrupt
inputs:
INTR,
RST
5.5, RST
6.5,
RST
7.5, and
TRAP.
INTR
is
identical
in
function to the
8080A INT.
Each of the three
RESTART
inputs,
5.5,
6.5,
and
7.5,
has
a
programmable
mask.
TRAP
is also
a RESTART
interrupt
but
it is
non-
maskable.
The three maskable interrupts
cause
the
internal execution
of
RESTART
(saving
the
pro-
gram
counter in the
stack and
branching
to the
RESTART
address)
if the
interrupts
are
enabled and if the
interrupt
mask
is not
set. The
nonmaskable
TRAP
causes
the
internal
execution of a
RESTART vector
independent
of the state
of
the
interrupt
enable
or masks.
(See Table
1.)
There are
two different
types of inputs
in the
restart interrupts.
RST
5.5 and
RST
6.5 are
high
level-sensitive
like
INTR (and
INT
on the
8080) and are
recognized
with
the
same
timing
as
INTR.
RST 7.5 is
rising
edge-sensitive.
For
RST
7.5,
only a
pulse is required
to
set an internal
flip-flop
which
generates
the
internal
interrupt request.
The RST
7.5
request
flip-flop
remains set
until
the
request
is
serviced.
Then it is resel automatically.
This
flip-flop
may also
be reset
by
using
the
SIM
instruction
or by issuing
a RESET
IN to the
80C85. The RST
7.5 internal
flip-flop
will
be set
by a
pulse on the
RST
7.5
pin even
when
the
RST 7.5 interrupt
is masked
out.
The status of the
three
RST interrupt
masks
can only be
affected
by the
SIM
instruction
and RESET IN.
The interrupts
are
arranged
in
a fixed
priority that
determines
which
interrupt
is to
be
recognized if more than
one is
pending
as follows:
TRAP
-
highest
priority,
RST
7.5,
RST
6.5,
RST
5.5,
INTR
-
lowest
priority.
This priority
scheme
does not
take
into
account the priority
of a routine
that
was
started by a higher
priority
interrupt.
RST
5.5
can
interrupt an
RST 7.5 routine
if the
interrupts
are
re-enabled
before
the
end
of the
RST
7.5
routine.
The TRAP interrupt
is
useful
for
catastrophic events
such
as power failure
or
bus
error.
The
TRAP input is recognized
just
as any
other
interrupt but
has the
highest
priority.
It
is not
affected by any flag
or mask. The
TRAP
input is both edge
and level
sensitive.
The
TRAP
input
must go high and
remain
high until
it is acknowledged.
It
will
not
be
recongized
again
until it goes
low, then
high
again.
This avoids
any false
triggering
due
to
noise
or
logic glitches. Figure
3
illustrates
the
TRAP interrupt
request
circuitry
within
the
8085.
Note that the servicing
of any
interrupt
(TRAP, RST
7.5,
RST
6.5,
RST
5.5, INTR)
disables
all
future interrupts
(except
TRAPs)
until
an El instruction
is executed.
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