Radio Shack 26-3801 - Page 39

36-
external
THAI"
INTERRUrT
REQUEST
INSIDE
THE
80C85
SCMMHT
rntoG&A
?>
lP
fir
CLEAR
interrupt
REQUEST
INTERNAL
TRAR
ACKNOWLEDGE
Fig.
3
TRAP
and RESET
IN
CIRCUIT
The
TRAP
interrupt is
special
in
that
it disables
interrupts,
but preserves the
previous
interrupt
enable status.
Performing
the first RIM
instruction
following a TRAP
interrupt
allows
you
to
determine
whether interrupts
were
enabled or
disabled
prior
to the TRAP.
All
subsequent
RIM
instructions
provide
current interrupt
enable
status. Performing a
RIM
instruction
following INTR, or RST
5.5-7.5 will
provide
current Interrupt Enable
status,
revealing that
Interrupts are disabled.
The
serial I/O
system is also
controlled by
the
RIM
and SIM
instructions. SID
is
ready
by
RIM,
and SIM
sets
the
SOD
data.
(d)
BASIC
SYSTEM
TIMING
The 80C85
has a
multiplexed Data Bus.
ALE
is
used as a
strobe to sample
the lower 8-bits
of
address
on
the Data
Bus. Fig. 4 shows an
instruction
fetch, memory
read and I/O
write
cycle
(as
would occur
during processing
of
the OUT
instruction).
Note
that during the I/O
write
and
read
cycle that the I/O
port
address is
copied on
both
the
upper and lower half
of
the
address.
There
are
seven
possible
types of
machine
cycles.
Which
of these
seven
takes place is
defined by
the
status of
the three
status
lines (IO/M,
Si
,
So
)
and the
three
control signals
(RD,
WR, and
INTA).
(See
Table
2.)
The status
lines
can be
used as
advanced controls
(for
device
selection,
for example),
since
they
become
active at
the
Ti
state, at
the
outset
of
each
machine
cycle. Control
lines RD
and
WR
become
active
later, at
the time
when the
transfer
of
data is
to take
place,
so
are
used as
command
lines.
A
machine
cycle normally
consists of
three T
states,
with
the
exception of
OPCODE
FETCH,
which
normally has
either
four or
six T
states
(unless
WAIT or
HOLD states
are
forced by
the receipt of
READY
or
HOLD
inputs). Any
T
state
must be
one of ten
possible
states,
shown in
Table 3.