Radio Shack 26-3801 - Page 54

(b)
Receiver
Operation
Data
is
received
in
seriai
form
at the
RInput.
When
no
data
is
being
received, RInput must
remain
high.
The
data is
clock through
the
RRClock. The clock
rate
is
1
6
times the data
rate.
(A)
A
low
level on
DRReset clears
the
DReady line. (B)
During the first stop bit
data
is
transferred
from
the
receiver register to
the RBRegister. If the
word is less than
8
bits,
the
unused
most
significant bits
will
be
a
logic low.
The
output
character
is right
justified
to
the
least
significant
bit
RBR1.
A
logic
high on
OError
indicates overruns.
An
overrun
occurs
when
DReady has
not
been
cleared before
the
present
character was
transferred
to
the
RBRegister. (C)
1
clock
cycle
later DReady is
reset to a
logic high, and
FError
is
evaluated. A
logic
high on
FError
indicates an
invalid stop
bit was
received,
a
framing
error.
A
logic
high on
PError
indicates
a parity
error.
-BfCINNtNG
OF JIMTSTO*
tit
*'
i
'
m
*Mi.f. at, ri
y
.
—.)»
CLOCK CYCLES
°""
'
lU
—
———
_
RECEIVER TIMING
u
0.
u
!
r
(NOT
TO
SCALE)
!
—4
—
i
clock cvcli
Fig. 16