Radio Shack 26-3801 - Page 55

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(c)
START
Bit
Detection
The
receiver uses a
1
6X
clock for timing.
(A)
The
start
bit could
have
occurred as much
as
one
clock
cycle before it was detected,
as
indicated
by
the shaded portion. The center
of
the
start
bit is
defined as clock count 7-1/2.
If
the
receiver clock
is a
symetrical
square
wave,
the
center of
the start bit will be located
within
±1/2
clock cycle,
±1/32
bit or
3.125%
giving
a
receiver
margin
of
46.875%.
The receiver begins
searching for the next
start bit
at
the
center
of the first
stop bit.
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Fig.'
17
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(d) IM6402
Pin
Functions
Symbol
Description
Vcc
Positive Voltage
Supply
NC
GND
RRD
RBR8
No Connection
Ground
A
high
lever en
RECEIVER
REGISTER DISABLE forces the
receiver holding
outputs RBR.1—
RBR8
to a
high
impedance state.
The contents
of the
RECEIVER
BUFFER REGISTER
appear
on
these three-state
outputs.
Word formats less
than
8
characters
are right
justified to
RBRi.