Radio Shack 26-3801 - Page 56

$2
Symbol
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
MR
Description
See Pin
5
-
RBR8
See Pin
5
-
RBR8
See Pin
5
-
RBR8
See Pin
5
-
RBR8
See Pin
5
-
RBR8
See Pin
5
-
RBR8
See Pin
5
-
RBR8
A high levei
on PARITY
ERROR indicates
received
parity
does
not match
parity
programmed
by control bits.
When
parity
is
inhibited
this output
is low.
A high level
on FRAMING ERROR
indicates the
first stop
bit was
invalid.
A
high level
on OVERRUN
ERROR
indicates
the
data
received
flag was
not cleared
before the
last
character
was
transferred
to
the received
buffer register.
A
high level
on STATUS FLAGS DISABLE
lorces
the outputs
PE,
FE,
OE,
DR,
TBRE to a high impedance state.
The
RECEIVER
REGISTER
CLOCK is 1
6X
the receiver
data
rate.
A
low level
on
DATA RECEIVED
RESET clears
the data received
output
DR
to
a low level.
A high
level
on DATA
RECEIVED
indicates
a
character
has
been
received and
transferred to
the
receiver
buffer
register.
Serial
data on
RECEIVER REGISTER
INPUT is clocked into the
receiver
register.
A high
level
on MASTER RESET clears PE, FE,
GE, and DR
to
a low level
and
sets
the
transmitter
output
to a high
level
after
18 clock cycles.
MR does
not clear the
receiver buffer
register.
This
input
must be pulsed at least once after power up.