At
the
same
time
228
stored
the
ASCII
word,
the
Divider Chain changed Video
RAM
addresses.
The
RAM
is
now
"looking"
for
the
next
ASCII
word. It has
exactly
six
dot
times
(about
560
nanoseconds in
64
character
format)
to
find it
before
the
Latch
is
commanded
to
store
the
next
word.
227
is
a smaller latch
that
operates
exactly
the
same as
228.
But instead
of
ASCII, it handles
the
graphic bit and blanking data. Pin 4
is
tied
to
the
inverted
output
bit
from
263,
the
graphic
RAM. Pin 5
of
227
has signal BLANK*
tied
to
it.
L8
is
tied
to
pin
12
and
our
"sneaky"
bit,
bit
6,
is
tied
to
pin 13
of
227.
All
of
these signals
are latched
into
227
at
the
same
time
as
the
ASCII
word
is
latched
into
228.
Each
input
to
227
has a
different
function.
The
graphic
bit
to
pin 4
of
227
will
determine
if
the
ASCII
word
contained
in
228
is
an alphanumer-
ic
character
or
is
a graphic word. Pin 5
of
227,
is
signal BLANK*. This signal comes from
230,
pin 10, and
controls
the
upper, lower, left
and
right boundaries
of
the
video display. When
B
LAN
K*
is
high,
the
CRT's electronic beam
is
allowed
to
draw
on
the
screen. When B
LAN
K*
is
low,
the
beam
is
in
a
boundary
area
so
it
prevents
the
beam from drawing anything.
L8
is
connected
to
pin 12
of
227.
L8
acts
somewhat
like BLANK*. L8, remember, specifies where
the
electron beam
is
located
in
any character-
line. When low, L8 allows
the
beam
to
output
alphanumeric
dot
data. When high,
L8
shuts
off
the
beam because
it
is
now
scanning
one
of
the
five scan lines between
character
lines.
The
last
piece
of
data
comes
into
227
at
pin 13. Sourced
at
230,
pin 13, this
is
the
"sneaky
bit"
that
is
derived from
data
contained
in
RAMs
263
and
262.
This
is
the
only
bit
at
227
which
could
be
considered
part
of
the
ASCII
word.
The
output
is
applied
to
Character
Generator
229,
at
pin 1.
Notice pin 1
of
both
data
latches. This
input,
when low, will force
the
latches
to
their
clear
state
(zero
at
the
outputs).
This signal
is
called
VCLR* (Video Clear) and
is
sourced by D flip-
flop
27,
at
pin 6.
The
flip-flop disables
the
data
latches during a
CPU
interruption
of
video
RAM. Notice pin 4
of
27.
It
is
tied
to
VID*.
When VID* goes low,
27,
pin 6 will go low.
The
low
at
pin 6 will clear
the
data
latches. (This
is
what
generates
the
black streaks we discussed
in
the
Video
RAM
Addressing section.) When
the
CPU has finished with Video RAM, pin 4
of
27
goes back high.
The
next
time
data
is
to
be
latched
into
227
and
228,
27
will toggle back
to
its normal reset
state
and allow
the
data
latches
to
operate.
If
27
was
not
used, we might see
characters
that
appear
ripped
apart
on
the
screen.
For
example, assume
the
CRT was draw-
ing a
character
when
the
CPU
took
command
of
Video RAM.
After
the
CPU finished,
the
Video Processing circuit may still see
the
ASCII
code
that
was in
the
latch
at
the
time
the
CPU
suddenly
jumped
in.
The
video circuit would
try
to
redraw
the
character
on
the
screen.
We
would
then
either
see
the
character
twice;
or
half
of
it would be over there, and
the
other
half would be here! Clearing
out
the
data
latch
insures
that
the
Video Processor does
not
get
confused.
35
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