A.
FUNcnONAL
SPECIFICATIONS
The
Model
Il
Fleppy Disk Controller (FOC) Board has baen
redesigned
ta
take advanlage
of
a new chip
set.
the
W01691
and
W02143.
This chip set provides more flexible write
precompensation (conlinuously adjustable from
1;\
ns
la
350 ns)
and a simpler adjustment procedure lor Ihe dalalcJock recovery
circuit.
The new design provides
two
independent drive inlerlaces.
one lor
the
internai drive and
an
additianal interface for up
ta
Ihree exlernal drives. This
aHaws
the system
ta
slarl·up
properly without damage to
the
system diskette even if the
external drives are
not
turned on.
There is also
no
need for
the
disk terminaler adaptor. currently
required for single-drive systems. A provision
to
generate a
software master
resello
the
W01791 was also added
(an
OUT
inslruction
to port
EBH).
This allows recovery Irom hang-up
conditions
which rarelyoccur ln
the
W0179X family parts.
The
redesigned
FOC
board
Is
fully soltware campalible wilh
the
previous design. wilh Ihe exception Ihat
an
additianal port
is provided lar Ihe saltware master resel funclion. A redesign
of lhe inlernal disk cable syslem is reqUired. sînce Ihers are
naw Iwo Independent
Elrive
interfaces. Field upgrades with
redesigned FOC boards will also require
the
new
cable syslem
ta
be
installed.
B.
THEORY OF OPERA
noN
Decodlng
loglc
The FOC-PAINTEA INTERFACE BOARD is
an
110
(inpul-oul,t
ut)
port map device wnich ulilizes ports
E0H.
El
H,
E2H.
E3H.
EuH.
E5H,
E6H. E7H, E8H and
EFH.
Table 1 summarizes Ihe port allocation lor
the
1I0ppy
controller
board.
Port-mapped devices use anly Ihe lower eight addrfSS
bits la sp&cify whlch port is being addressed.
The
upper eight address bils
are
ignored completely and s
re
nal
relevant
10
por(-mapped devices.
nuee
olher sigm!ls
(WA·.
AD'
and lOCY') are used
by
port-mapped devices
ta
datermine whelher
an
1/0 operation is la accur. lf
WA'
a.,d
IOCYC'
are
both
law,
Ihis
condition
deflnes
an
aUI,tut
aperalion in progress.
Figure 6
(FOC
schematic diagram) should now
be
relerrad la
for
the
remainder
of
Ihe Oeeodlng Logic discussion.
U21, pin
B.
is Ihe oulpul
of
a four-input NANO gale. This l'ln
should be low when any
01
the
ports E0H through
EFH
é
ra
being addressed. U21, pin
6.
is also
an
oulput
01
a
lour-in~
ul
NANO
gale
which
shauld
go low when the
pori
belilg
addressed cantains
an
F HEX
in
Ihe low·order nibble
01
tle
port address.
Table
1.
Port
AllocaUon
PORT
#
ALLOCATION
fUNCTION
E0H
Pla
Port A -
Data
Printer and
fOC
INT.
status
E1H
PlO Port B -
Oata
Printer
Oat<l
(output)
E2H
PlO Port A - Control
Configuring Port A
E3H
Pla
Port B - Control Configuring Port 8
E4H
FOC
Status/CMO
Register
FOC
Status
and
CMO
E5H
FOC
Track Register
Current Track Add.
E6H
FOC
Sector Register
Current Sector Add.
E7H
FOC
Data
Register Data To
or
From
Oiskette
EaH
Soft
fOC
Resel
Out
Resets
fOC
EFH
Drive
Select
Latch Drive, Mode,
Side
Select
1
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