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Radio Shack TRS-80 II
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ln cIolIblEroensily mode (ODEN = 0), the signais EARLY and
LATE
are used
10
select a phase input
(01'-04')
on
the leading
edge of WDIN. The
STe
lina is lalchad high when this occurs.
causing
the
WD2143 to slart ils pulse generalion. 02· is used
as
the
wrile
data
pulse
on
nominal
(EARLY=
LATE = Il). 01"
18
used lOf the early and
03'
tS
used lor the laie.
The
leading edge of
04'
rasets
the
STe
lina in anHcipalion of
the
neX!
dala pulse. When TG43 = 0 or
DDEN:
1,
precom-
pensation is disabled and any transitions on the WOIN line will
eppear
on
the WOQUT lina.
When
VFOE'
and WG are (ow, the
dock
recovery circuits are
enabled. When
the
RDO"
line goe5 low, lhe
PU
or
PD"
signais
will become active.
Il
the
ROC"
line ha5 made Ils transllion in the beginnlng
01
the
RCLK window,
PU
will
go
Irom a high impedance stale
to
a
loglc one, requesting
an
Increase in VCO frequency. Il the
ROO"
line has made its transition
at
lhe end ot the
RClK
window,
PU
will remain in
the
high impedance slale while PO'
will
go
to
a lagic zero, requesling a decrease in
the
VCO
frequency.
When lhe leading edge
01
ROO' occurs in
the
center
01
the
RCLK window, bath
PU
and
PO"
will remain
in
lhe high impe-
dance slale, indicating that no adjustmenl ot lhe VCO Ire-
quency is required.
By tying
PU
and
PO"
together.
an ad
just-
ment signal is created which will be
forcecl
low lor a decrease
in
VCO
Irequency and lorcecl high
lOf
an
increase in
VCO
Irequency.
To speed up rise limes and stabîlize the output voltage. a
resislor dîv\der, usîng
R2.
A21
and A24, is used
to
adjusl lhe
tri-stale level
al
apprOlcimately 1.4V. This adjuslment results in
a worsl case
voilage swing ot
+!
-1V,
which
Îs
acceplable lor
the
Irequency control input of
the
VCO (U24).
This signal derived Irom
the
combination
01
PU
and PD" will
eventually correct
the VCO input to exactty
the
same frequency
multiple as
the
AoO" signal.
The
leading edge
01
the AOD·
signal will then occur in
the
exact center
01
the
AClK
window,
an
ideal condition for the
1791
internai recovery circuits.
wo
,
,
no
woo~
"'
---
VFOE/WF
tG.J
..,
'"
"
"
"
"
"
"
"
"
'"
B-
RelK
CONTROL
H
..
1
r
2.-:/
'u
cow
pvcc
.,
P"'U
FIL
rEJl
ODEN
P"
,...-
."
pLAn
PEARL'!'
1-
~T(;4J
g.,o
..
--
PIIECQM
POCH"
"'FOE
"'FOE
-
lOGIC
"
..
,W,
OEl'IUX
ClOClC
p.o
"
..
p.u
rr=
,
.0
PRCLK
E""LY
LATCM
1
WCI
..
p~
"""'"
L"'H
WODUT
'"
Figure
1,
WD1691
Block
Dlagr.m
5

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