These two outputs, labeled XF'
and
EX', are combined
at
pins
4
and
5
01
U22. U22.
pin
6
Is
Ihe decoder lor
the
drive-select
(U11)
mapped
at
port EFH. This oulput is combined
witt'!
our
at
U22, pins 9
and
la
ta
produce Ihe signallabeled
DRVSEl'
at
U22,
pin
B.
The rising edge
01
DRVSEL" is used
by
pin 9 of
un
ta
latch
the data present
on
the internai data
bus
corresponding
ta
an
output ta pon
EFH.
This data pattern is used
ta
determine the
drive, mode,
and
side selection. The bit allocation for this laten
is detailed
in
Tlble
2.
The signal labeled
EX'
is used
as
an
enable
10
gate Ihe
addresses
A31
and
A21
to
the control inputs
01
U23 (Binary
ta
Decimal Decoder.)
The
slgnats
A31
and
A2t.
atong with
At!
and
AQt
lorm the inputs
to
the
decoder
U23. U23,
pins
1.
2.
3.
4.
5.
6.7.9
and
10
are
the
outputs which produce Ihe
ehip
enabtes
lor the PlO,
FOC,
and
soit reset
togie.
The pon decode tabeted
ES"
is combined with
the
signal
our
at
U34
pins 1
and
2.
The resultlng signal Irom
U34
pin.
3 is
combined with RE$ETI'
al
U14,
pins
12
and
13.
The output
01
U14,
pin
11
is a tow-going strobe which resets
U1S
if
an
output
ta port
EBH
is exeeuted or
the
front"panet reset switch is
actuated.
CPUIN is a signal generated
by
the decoding logic for
the
purpose
01
switchlng
the
direction of the data
bus
transceivers
(U30.
U31)
in
preparation lor
an
input operation.
There
are
two conditions which require
the
data
bus
trans-
celvers
to
switch direction such that they drive data outward
10
the system data bus:
(1) Port input operation
(2)
Inlerrupt acknowledge cycte
The port-input operation is
detected by the combination of
Bny
01
the ports
EOH
through E7H being addressed concurrer
Uy
with
an
Input operation
in
progress.
U34,
pin
'11
will
go
low when this condition
is
deteeted. Il
SYNCI'
and
IOROI'
are
both
tow.
this condition indicates
an
interrupt acknowtedge cycle is in progress and Ihat t1e
înterrupting device should present
ils vactor
to
the data
bus.
Intermpl priority
15
determined by Ihe signallEtN (pin
13
01
t;'le
system bus).
If
IEIN
is hlgh during
an
inlemJpt acknowtedge cycle,
no
device
01
higher prlorlty is requesting service and
the
requesh
19
device may bring ils lEOUT
tow
to
prevent devlces of
10'A
er
prjority Irom receiving service. A high
on
pin 1
of
US
indicates
an
inlerrupt acknowtedge cycle
Is
in
progress. A hign
on
pir 2
of
U5
indicales
no
higher priority device is requesting service.
A high on pin t 3
01
US
indlcales a device
on
Ihis board is
requestlng service.
Il ail these conditions are true,
pin
12,
US
(INTAK') will
go
JON.
This output is combined with the output Irom pin
11
of
U13
al
pins 4
and
5
01
U14.
If eilher pin 4
or
pin 5
of
U14 goes
ION.
then pin 6
01
U14 will also
go
low.
U2
inverts this signal and
"in
1201
U2
will go high (CPUIN). Il CPUtN is high, the dala
bJS
transceivers disabte their receivers
and
enable their drivers
to
gate data onto
the
system data bus. This allows
the
PlO
10
transfer ils inlerrupt vector
to
the CPU.
Table
2.
BIT Allocation
Port EFH, Drive
Select Latch (output only)
07
06 05
O,
03
02
01
De
Mode Select
Side Select
Ulll,lsed Ullused
DRV3SEl
DRV2SEl
DAV1SEl
DRV0SEl
t'J"
FM
Mode
0"Side
1
1"
NOTSEL
1'"
NOTSEL
,
..
NOTS
El
,
"NOTSEl
1'" MFM Mode
1::Side0
0"
SEL
~::
SEL
0"
SEL
~
'"
SEL
NOTE:
D3
lhrouqh D0 - only
one
of
these
bits should
be
low
per output instruction.
2
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