Renesas RL78/D1A - Note on Self-Programming for Flash-Memory; State of High-Speed on Chip Oscillator During On-Chip Debugging; Setting of Download Mode (RL78;FGIC[RAJ240100])

E1/E20/E2/E2 Lite Additional Document 3. Notes on Usage
R20UT1994EJ0910 Rev.9.10 Page 56 of 59
Oct.06.23
3.10.14.6 Reset for reprogramming Internal RAM
For RL78/F2x devices, the following area in internal RAM will be reprogrammed if reset is applied during
program execution.
0xFF5F8 – 0xFF820
Please write program data on the area with the user program after reset if program data is allocated in this
area.
3.10.15 Note on self-programming for flash-memory
Please DO NOT use the first 128 bytes of internal RAM as debugger will use when satisfying the following
both criteria
- using RL78/G2x and RL78/F2x series devices
- selecting [Yes] in [Program uses flash self programming] under [Flash] on [Debug Configurations].
3.10.16 State of high-speed on chip oscillator during on-chip debugging
During on-chip debugging, high-speed on-chip oscillator will be oscillation state regardless of any CPU
operation mode or any value is set on the bit0[HIOSTOP] of CSC register.
Please be careful peripherals which are supplied clock source apart from CPU will remain in operation
similarly. The peripherals such as 32-bit interval timer (TML32) or Logic and event link controller (ELCL) for
RL78/G2x series are the example.
3.10.17 Setting of download mode (RL78/FGIC[RAJ240100])
On RAJ240100 which is one of RL78/FGIC, please select download mode to "Data priority". If "Speed
priority" is selected, a part of data will be deleted and the chip cannot be used.