RL78 Family VDE Certified IEC60730/60335 Self Test Library
R01AN0749EG0201 Rev.2.01 Page 23 of 50
Mar 04, 2014
The principle behind the hardware measurement is based on the input capture measurement of the reference clock in the
appropriate TAU channel. As this is a hardware capture measurement the time captured is the “period” of the reference
clock as a of the system clock. This is a more accurate method of measurement than the software approach.
The measurement sequence is
• Synchronise to the reference clock (Wait for first capture event)
• Wait for the next capture event
• Compare the value in the capture register against the high and lower limit reference values
The test harness provides an example based on the following settings
System clock = 32MHz
Reference Clock = 32KHz
Therefore the calculation is simply 32000000 / 32768 = 976 (h’3D0)
An allowance should be made for capture value variances in the upper and lower reference values
2. Software Measurement
The principle behind the software measurement is based on a software counter measuring the transition on the test port
pin. The actual comparison values can be a mix of calculation and measurement as it is difficult to fully calculate the
measurement value due to variances in the synchronisation and monitoring of the input state.
The measurement sequence is
• Synchronise to the reference clock (high to low transition on the input pin)
• Wait for the next low to high transition and then start the software counter
• Increment the software count until the next high to low transition
• Compare the software count value against the high and lower limit reference values
The basic calculation is based on the following equation
System Clock / (Reference Clock / 2) x the number of clock cycles executed in the count loop
Note: The measurement period of the software counter is based on half the reference clock
Using the example settings provided in the test harness project
The System clock is 32MHz and the reference clock is the Sub Clock 32KHz then the calculation is
32000000 / (32768 / 2) x Loop Count
The cycle count can be calculated as shown in the code extract in figure 8 below
½ the reference clock = 15.26uS (32KHz / 2)
The loop count of the measurement period (measure high time) is 6 clock cycles
At 32MHz this is 187.5nS (6 x 31.25nS)
Therefore the approximate software count for the test harness example is 15.26uS / 187nS = 82 (h’52)
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