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Renesas RL78 Series Application Note

Renesas RL78 Series
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RL78 Family VDE Certified IEC60730/60335 Self Test Library
R01AN0749EG0201 Rev.2.01 Page 25 of 50
Mar 04, 2014
Table 12: Source files: Software Clock test
STL File name Header Files
stl_RL78_sw_clocktest.asm stl_clocktest.h
stl.h
Test Harness File Names Header Files
main.c
stl_global_data_example.c
stl_main_example_support function.c
stl_peripheralinit.c
main.h
stl_gobal_data_example.h
Declaration
bool stl_RL78_sw_clocktest(void)
Description
This function tests the system clock using a software measurement (software counter) process. The measured result
(software count) is compared against the upper and lower limit values defined in the clock test header file
(stl_clocktest.h), and the result status (Pass / Fail / No reference clock) is returned to the calling function.
The reference limits calculation is based on the following
System Clock / (Reference Clock / 2) x times the number of clock cycles executed in the count loop
The function “indicate_test_result.c” will be called by the test harness control files (main.c) to process the test result
Note Function “indicate_test_result.c “is located in the module stl_main_example_support function.c
Input Parameters
swMAXTIME
Upper time limit compare value (Defined in stl_clocktest.h)
swMINTIME
Lower time limit compare value (Defined in stl_clocktest.h)
TESTPORT
Test Port Input Pin for external reference signal input (Defined in stl_clocktest.h)
Output Parameters
NONE
N/A
Return Values
bool
Test status result returned in CPU register A
0 = Test passed.
1 = Test measurement failed (Outside the reference window)
2 = Test failed (No reference clock detected)

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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