Roland SDE-3000 Service Notes

SDE-1000/3000
FEB. 5,1984
MSCK, HDCK & CLOCK GENERATOR
The frequency of Clock Generator is as follows (approx):
2.7MHz at Normal 1.7MHz at TIME X1.5
2.7M-3.3MHZ at MOD max. 1.7M-2MHz at TIME X1.5/M0D max.
MSCK - Clocks the internal Timing Generator that
times the most of digital circuits.
HDCK - The frequency of HDCK is MSCK or 43Hz at normal mode.
Used by the CPU as a time base for calibrating Delay Time display.
The CPU fails to read switches and jacks if HDCK period is outside
7m-50ms.
RAM 1-RAM 3
12-bit data read from three RAMs are fed through these pins to internal
three shift registers for temporary storage. All the buffered bits are placed on
D0-D11 at a time to form a 12-bit parallel data to be applied to D/A con
verter for reproducing a part of delay signal.
During HOLD ON the A/D converter remains active but cannot receive
input signal. The comparator output is inhibited from being written into
RAMs.
CONTROL SIGNALS IN DIFFE RENT MODES
RAMs(IC9-IC11)
Record the results of Successive Approximation, from MSB (D11) to LSB
(DO), sharing 12 bits - 4 specific bits for each as shown in the table at the
beginning of General Description.
CPU
The CPU is provided with a battery backup to retain switch, delay time and
preset settings.
TO - Decides the operation mode of the CPU:
+5V--
0V--
SDE-1000
- SDE-3000
T1
— Receives Clock pulses through IC12 HDCK pin. The clock serves
as a time base to enable the CPU to calibrate Delay Time Display
and is ignored by the CPU when Modulation is ON and MOD
Foot control jack disengaged. (See HDCK, Main Controller.)
P20 (DATA) - Send memory access control data after every delay time
P21 (SHIFT) - settings (see DATA/SHIFT, Main Controller).
P23 -
P10 -
P11
P12 -
P13 -
P14 -
P15
P16
P24
P2'7
DB7
DBO
DB3
DB4 -
DB5
NOTE:
Becomes "L" for muting.
(See timing chart in DATA, SHIFT, Main Controller.)
Read SW1-SW10 through the matrix in combination with P24-
P27 and DB7.
Input from PRESET SHIFT jack. A rising edge of this input steps
PRESET memory.
MODULATION FOOT CONTROL jack input.
With MODULATION ON and this input at low, CPU ignores T1
input. For example, rotation of DELAY TIME X1-X1.5does not
change TIME display.
HOLD jack input.
When H, readings of TIME UP or DOWN and PRESET memory
are inhibited.
PLAY MATE jack input. Active rising edge.
Rising edge from this pin latches the following logic codes made
by DB0-DB3 into Analog Control IC17.
TIME X2, DELAY PHASE, MOD and FEEDBACK
Output of switch scan signals which are read through P10 and
P11.
Besides Control signals for IC17, these pins deliver numerical
data to fluorescent display via IC18 7-seg-decoder.
DB6: Dot Point signal.
Send LED lighting signals.
When P10, P11, P12 and P15 pins receive signals almost at the
same time, the CPU gives priority to the signal first read. Example:
PRESET SHIFT and Front Panel switches are disabled when PLAY
MATE has been activated.
10

Roland SDE-3000 Specifications

General

Type	Digital Delay
Output Impedance	1 kOhm
Inputs	1/4" phone jack
Outputs	1/4" phone jack
Total Harmonic Distortion	0.05%
Power Supply	AC 117 V