PRINCIPLE OF OPERATION cont.:
The PHASE DETECTOR compares two signals, a variable frequency f
rence f+equency fR,. The reference frequency fR1 is the IO MHz
divided down to 1 kHz.
The variable frequency fV1 is generated from the VCO frequency fL0, in the
following way:
In the LOOP
1
MIXER the counter frequency fTl is produced as the difference be-
tween the VCO frequency fLO, and the frequency fHARM which is a multiple of 2
MHz derived from the 10 MHz TCXO.
fT1
= fLOl - fHARM = fLOl
- (m x 2 MHz)
q
N1 x 1 kHz
For each 2 MHz band a new fLOl and fHARM is selected by the BAND CONTROL UNIT,
and it always results in a 2 MHz variation of the frequency fTl to PROGRAMMABLE
DIVIDER.
The frequency fT1 is divided down by a dividing figure NJ in the PROGRAMMABLE
DIVIDER to the variable frequency fV,.
fVl z fTl/Nl = 1 kHz
The working principle in a phase locked loop is as follows:
A frequency error between the variable frequency fV1 and the reference fre-
quency fRl will via the PHASE DETECTOR and the LOOP 1 FILTER cause a DC
control voltage controlling the VCO frequency and consequently the variable
frequency fV1 so that fV1 follows the reference frequency fR1 in frequency.
fR1
=
fVl
q 1
kHz
The VCO frequency fL0, is now phase locked on a fixed frequency to the re-
ference frequency fRJ and has therefore the same accuracy as this.
Changing of the VCO frequency fLO1 by 1 kHz is carried out by changing the
dividing figure N1 in the PROGRAMMABLE DIVIDER by one.
fLol
q
fHARM + (N, X 1 kHz)
Principle of programming:
The PROGRAMMABLE DIVIDER contains a counter circuit counting down from a
start figure 2000 + PI and stops at the stop figure St. Each time the coun-
ter reaches the stop figure S,,
a pulse (fV1) is fed to the PHASE DETEC-
TOR, and the counter starts counting down again from the start figure 2000 +
PI. Division of fTl by N1 is now achieved.
l
fv, = fT,/N,;
N, = 2000 + P1 - S1
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