Sansui MC-X7 - IC Functions and Block Diagrams (Continued); TC4053 BP (Multiplexer) Function Details; CXD2500 Q (Digital Signal Processing) Function Details

® TC4053BP (3-Circuit 2-Channel Multiplexer)
26
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* CXD2500Q (Digital Signal Processing)
Digital PLL
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EMPH 69)
SQCX 67
a CESAR
MON (3)
snaper
Subcord
Processer
(7) VCKI
Vari-pitch
Demodulator
double
speed
ivan
SYNC
Protector’
Timing
WFCK o— Fn Generator!
SCOR 63)
EXCX 65 Subcord
Gili, aee Processer
EFM
(9) VPCO
Register
¢ Truth Table <TC4053>
|
io)
32x RAM
MC-X7/X7L
<Compact Disc Player Section>
MC-X7/X7L
<Compact Disc Player Section>
CONTROL INPUT
ra
L
“ON”
ANNEL
OX, OY, 02
o<
—
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2)
MN
Adress Prio rity
|
D/A
(Data Processer
—
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Vooe
Yss
Vss
PSSL
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ies oversmpling
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Error
Corrector
data
sequencer
Servo
¢ Terminal Function <CXD2500Q>
in No, | Pin tame [0
Eo OK Ie Focus OK input terminal
FSW Time-constant switching output for the output
filter of spindle motor .
3 | Mon fol ON/OFF control output of spindle motor
4 Drive output of spindle motor. Rough control in
CLV.S mode and phase control in CLV.P mode
MDS Drive output of spindle motor Speed control in
CLV.P mode
LOCK. This pin samples GFS signal by WFCK/16 and,
if “H”, issues “H”.
If “L” occurs consecutively 8 cycles, “L” is output.
VCOO VCO output. When it is locked at EFM signal,
f = 8.6436 MHz.
8 [wor fi |veomme SS
io
[est
fey
Charge pump output for pulling up analog EFM
signal
| 16 VPCO gee PLL charge pump output for variable pitch
17 VCKI Clock input for variable pitch. f = 19.0934MHz
18 FILO Filter output for master PLL
19 FILI
co
Filter input for master PLL
Charge pump output for master PLL
ae
VCO control voltage output for master PLL
EFM signal input from EF amplifier
BG
2/2
z
27 Full swing Output of EFM signal
30
ASY
PSSL
O
Audio data output mode switching output.
Serial output at “L”. Parallel output at “H”.
Strobe signal output. 176.4 kHz when DF is ON.
88.2 kHz when CXD11250 or DF is OFF.
LRCK Strobe signal output. 88.2 kHz when DF is ON.
44.1 kHz when CXD1125Q or DF is OFF.
23 | veo |—[ Power supe (25 V)
DA16 (MSB of parallel voice data) is output when
PSSL = “H”. DATA is output when PSSL = “L”,
DA15 DA15 is output when PSSL = “H”.
Bit clock of 48 bits is output when PSSL = “L”.
DA14 DA14 is output when PSSL = “H”.
Serial data is output when PSSL = “L’.
37 | DA13 DA13 is output when PSSL = “H”.
Bit clock of 64 bits is output when PSSL =“L”. -
38 DA12 DA12 is output when PSSL = “H”.
LR clock of 64 bits is output when PSSL = “L”.
39 DA11 DA11 is output when PSSL = “H”.
GTOP is output when PSSL = “L”.
40 DA10 DA10 is output when PSSL = “H”.
XUGF is output when PSSL = “L”.
41
DAO9
DAO9
is
output
when
PSSL
=
“H’.
XPLCK is output when PSSL = “L”.
DAO8 DAO08 is output when PSSL = “H”.
GFS is output when PSSL = “L”.
43 DAQ7 DAO7 is output when PSSL = “H”,
RFCK is output when PSSL = “L’.
DAO6 is output when PSSL «= “H”.
C2PO is output when PSSL = “L’.
DAO5 DAOS is output when PSSL = “H”,
XRAOF is output when PSSL = “L’.
WDCK
44 DA06
E
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+
a
on
[Pinno.[ pinnae [vo[———Funaton
46 DA04 DA04 is output when PSSL = “H”.
MNTS3 is output when PSSL = “L”.
47 DA03 DA03 is output when PSSL = “H”.
: MNT2 is output when PSSL = “L”.
48 DA02 DAO2 is output when PSSL = “H”.
MNT1 is output when PSSL = “L”.
inl) DA01 (LSB of parallel voice data) is output when
50
PSSL = “H”.
MNTO is output when PSSL = “L”.
APTR O | Control output for aperture compensation.
“H” for R-ch.
51 APTL as
Control output for aperture compensation.
“H" for L-ch.
[ves [Yano
XTAI X'tal oscillator output. f= 16.9433 or 33.8688
MHz by selecting the mode.
54 XTAO X’tal oscillator output. f = 16.9344 MHz by se-
lecting the mode.
| 55 | XTSL ae 16.9344 MHz at L. 33.8688 MHz at H.
| 86 | Fst || 2/3 frequency divided output of pins 53 and 54
57 C4M Frequency divided output of X’tal. f = 4.2336
MHz. It changes at the same time as varying
the pitch.
C16M | 16.9344 MHz output. Simultaneously changes
when varying the pitch.
59 ON/OFF control of digital output.
ON and OFF at H and L, respectively. |
| 60 | DOUT || Digital output
61 EMPH Issues H or L when replaying disk is with or
without emphasis, respectively.
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68 MUTG Muting input. MUTG is “T” normal state or no
sound state when ATTM of the internal register
is “L” or “H”, respectively.
69 Issues the output of internal state according to
the address.
XRST aa System reset input. To be reset at “L”.
71 DATA ae Serial data input from CPU
2 Latch input from CPU. Data (serial data from
CPU) is latched to each register at the fall of the
signal.
Power supply (+5 V)
Serial data transfer clock input from CPU.
It latches data at the rise of locking signal.
Vop
CLOK
E
a
74
Tracking pulse input
Serial data transfer clock output to SSP
Mirror
signal
input
|
CNIN
DAT
XLT
CLK
76
77
78
79
10