Sanyo DC-007C - Page 31

IC BLOCK DIAGRAM & DESCRIPTION
ICI02 LC78622NE (Digital Signal Processor)
EFMO
TST11 TEST2 TEST4
WDO Was Plk3 ISET FR
PCK TAI TE3T1 TEST3 TEST5
VDO WE
VCOClockoscillator
RAMAddress
EFMIN
I
1
II I
av+
b
CLV
av-
3
Digital Sewo
VIP1
+
FSEO
Syrumous Detect
EFMDemodulation
InterpolalationMute
v
Sillingual
,
Cl C2 ErrorDetect&
CorreclControlFlag
c=’
I
Diiital Attenuator
I
1 1
I
t%
WRU
Smu-T
mm
COIN
RWC
HFLTESTWF JP- JP+~ TGL CfX7&NT&tJT5 El
L
I-/ lbti DAC ~
No. I Pin Name I LfOI
Function
1
I
DEFI
I
I ]Inpuf terminal for detect signal of defect
[“
Xtal Root
TimingGenerator
H ERO 16M42Mxv:~ XIN
Xvcn Rvm
RWl LCitC MVTEL
LVDCI
XOUT
RVSS MUTER
LVa.s
H
2 TAI
I
I IInput terminal for test.
3
PDO
I O lThe phase comparison output terminal for
I
I
I I
external VCO r%ntrol.
I
1!
4 VVss
I
- lGround terminal for built-in VCO
5
ISET
I IResistance connactiin terminal for
I
electric current adjustment of PDO output.
6 WDD
-
Built-in VCO power supply terminal.
7 FR I VCO frequency range adjustment.
6 Vss - Ground for Digital
9
EFMO
o EFM signal output terminal for slice level control.
10 EFMIN I EFM signal input terminal for slice level control.
11
TEST2
I TEST pin. Normal time is non connection.
12 CLV+ o Output terminal for Disc motor control.
13 I CLV- I O 10utput terminal for Disc motor control.
14 I v/P
I O lChange of rouh servo / Phasa control
I
floug~ servo :;’H”, Pha~ control: “L”
15 HFL I Input terminal of track search signal.
16
TES I Input terminal of tracking error signal.
17
TOFF o Ouiput terminal of tracking off.
18
TGL o Output terminal for change of tracking gain.
19
JP+ o Output terminal for traddng jump cmtrol.
al
JP-
I O 10utpuf terminal for tracidng jump control.
211
PCK I O lClock monitor output terminal for EFM data
I I
Ipkybsck. (4.3218 MHz)
221 FSEQ
I O 10utput terminal for detect of SYNC signal.
Z31 DVDD
I
- +5V
24 I CONT1 I VOI
z CONT2 I/o This output can cmtrol at serial control fmm
26 CONT3 m micro proceaaor.
27 CONT4 fto
a I CONT5 Iml
Z31 EMPH
] O 10utpuf terminal of cb-amphasis monitor.
I
“H”: de-emphasis
20 C2F o output terminal of C2 flag
3t DOUT
o Output terminal of digkal out
32 TEST3 I Test pin.
- 38
C2F
LOUT
(NC)
No. I Pin Name I lrO I Function
331
TEST4
I
I lTeat pin.
34
NC - Non connection.
35 MUTEL
o Mute output terminal for L-ch
3 LVDD
- Power supply for L-ch
37
LCHO
o Output terminal for L-ch
36 LVSS - GND for L-ch
33 RVSS - GND for R-ch
a
RCHO
o Output terminal for R-ch
41 RVDD - Power supply for R-ch
42 MUTER
o Mute output terminal for R-ch
43
XVDD - Power supply of crystal oscillation
44 XOUT
o Connection terminal of crystal oscillation(16.9344MHz[
45
XIN I Connadon terminal of crystal oscillation(16.9344MHz)
46
Xvss - GND of crystal oscillation
47 SSSY
o Output terminal for synchronizing signal of
sub-cord block
48
EFLG
o Output terminal for correction monitor of Cl, C2,
I
I I
Isinglaand Doubfe
I
491
Pw I O 10utput terminal for sub-cord of P, Q, R, S, T, U and W
ml SFSY I O 10ufput terminal for synchronizing signal of
I
sub-cord frame
51 SBCK
I Input terminal for readout clock of sub-cord
S?
FSX
o Outputterminal of Synchronizing signal (7.35kHz)
5.3 WRQ
o Outputterminal for stanrby of subcord Q output
54 RWC
I Input terminal of read I wtie control
56 SQOUT
o Output terminal of subcord Q
58 COIN I Input terminal of command from micro processor
57 CQCK
I Clod input for reading sub-cord from SQOUT
58
RES I Reset (turn on: L)
93
TST11
o Test pin
m
16M o 16.9344MHZ
6t
4.2M o 4.2336MHz
8? TEST5
I Test pin
63 Cs
I Chip select terminal
64 TEST1
I Test pin