Sanyo DC-DA3300M - IC Block Diagram & Description (IC251)

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IC BLOCK DIAGRAM & DESCRIPTION
16
1
15
2
14
3
13
4
12
5
11
6
10
7
9
8
VREF
MPXIN
Vdda
Vssa
FLOUT
CIN
TEST
XOUT
RDS-ID/ READY RDCL RDDA RST MODE Vddd Vssd XIN
Vdda
Vssa
MPXIN
TEST
TEST
VREF FLOUT CIN
XIN XOUT
OSC
Vddd
Vssd
RDDA
RDCL
MODE
RST
RDS-ID
/
READY
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
VREF
SMOOTHING
FILTER
+
-
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
RAM
(128bit)
RDS-ID
DETECT
CLK(4.332MHz)
PIN NO. PIN NAME I/O Description
1 VREF O Reference Voltage Output (Vdda/2)
2 MPXIN I Base Band (Maltiplex) Signal Input
5 FLOUT O Sub Careea Output (Filter Output)
6 CIN I Sub Careea Input (Comparator Input)
3 Vdda - Analog System Power Supply (+5V)
4 Vssa - Analog System Ground
8 XOUT O Crystal Oscillator Output (4.332MHz)
9 XIN Crystal Oscillator Input (External Reference Signal Input)
7 TEST Test Input
12 MODE Reading Mode Setting (0: Master, 1: Slave)
13 RST RDS-ID/RAM Reset (Straight Polarity)
14 RDDA O RDS Data Output
15 RDCL I/O
RDS Clock Output (Master Mode) /
RDS Clock Input (Slave Mode)
16
RDS-ID/
READY
O RDS-ID/READY Output (Negative Polarity)
11 Vddd - Digital System Power Supply (+5V)
10 Vssd - Digital System Ground
I
IC251 LC72723M (RDS Demodulation LSI)
IC446 KIA7805API (Regulator)IC443 BA7755A (Rec/Play Switch)
1 4 52 3
123
1. INPUT
2. COMMON
3. OUTPUT