Sanyo DC-F210 - Page 45

i
IC BLOCK DIAGRAM
.
IC101 CXA1782BQ [Servo
Siwal Processor)
L
Io.1 Namell/0] Function No. Name 1/0
Function
26
Cc2
o
Input pin for the DEFECT bottom hold output
capacitance-couDled.
1 FEO
o
Focus error amplifier output. Connection
internally to the comparator input.
1 , ,
2
I
FEI
I
I ] Focus error input. 27 I CCl I I I DEFECT bottom hold output.
I
Capacitor connection pin for detect time
3 FDFCT
I constant.
28
CB
,
Connection pin for DEFECT bottom hold
capacitor.
29
CP
, Connection pin for MIRR hold capacitor.
MIRR comparator non-inverted irmut.
—
+
Ground this pin through a capacitor when
I decreasing the focus servo high-
, External time constant setting pin for
Increasing the focus servo low freauencv.
FGD
4
$%==+
, Input pin for the RF summing amplifier output
RF summmg amplifier output Eye pattern
RF summing amplifier inverted input. The RF
5
FLB
6 I FE_O I O I Focus drive output.
1 , ,
7 FE_M I I I Focus amplifier negative input.
32 RF_M
I amplifier ga~n is determined by the resistance
connected between this pin and RFO pin.
33
LD
o APC(Auto Power Controller) amplifier output.
34
PHD
I APC(Auto Power Controller) amplifier input.
—
SRCH
I
External time constant setting pin for
generating focus servo waveform.
TGU
I
External time constant setting pin for
switching track-ing high frequency gain.
TG2
I
External time constant setting pin for
switching track-ing high frequency gain.
High cut off frequency setting pin for
FSET I focus and tracking phase compensation
amplifier.
TA_M I Tracking amplifier negative input.
8
9
T--” I I
RF I-V amplifier inverted input. Connect
35 PHD1
I these pins to the photo diodes A + C and B +
I
10
I
I D pins.
I
I RF I-V amdifier inverted input. Connect
11
36 ! PHD2 I 1 Ithese pins’to the photo diodes A + C and B + I
D pins.
37
FE BIAS I Bias adjustment of focus error amplifier.
12
—
13 TA_O
o Tracking drive output.
SP P
I Sled amplifier non-inverted input.
II
F I-V and E I-V amplifier inverted input.
I Connect these pins to the photo diodes F and
—
14
I
IE.
I
I F I-V and E I-V amriifier inverted input.
15
--t
SL_M I
SL_O O
I Sled amplifier negative input.
—
16
-
Setting pin for Focus search, Tracking II
I
Connect these pins to the photo diodes F and
E.
17
ISET I
40
El
I-V amplifier E gain adjustment. (When not
- using automatic balance adjustment.)
\
18 Vcc
I -
41 I VEE I - lGround
I
19 CLK I Serial data transfer clock input from CPU.
XLT
I Latch input from CPU.
DATA
I Serial data input from CPU.
42
TEO
o Tracking error amplifier output. E-F signal
outout.
—
20
21
43
LPFI I
Comparator input for balance adjustment.
(Input from TEO through LPF.)
~
22 XRST I Reset input; resets at Low.
23 C.OUT O Track number count signal output.
Outputs FZC, DFCT, TZC, Gain, BAL, and
24 SENS O others according to the command from
44
TEI
I Tracking error input.
45
Window comparator input for ATSC
ATSC I detection
CPU.
25 FOK
o Focus OK comparator output.
46
-fzC
I
Tracking zero-cross comparator input.
Capacitor connection pin
for defect time
47
TDFCT I constant
I I
1
48 I VC O I (VCC + VEE) / 2 DC voltage output.
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