Sanyo DC-F210 - Page 47

IC BLOCK DIAGRAM
IC104 CXD2508AQ (Digital Signal Processor)
No. I Pin Name I UO I
Function
I
No. I Pin Name I l/O
I
Function
I
1
I
SCOR O Turns [H] when sync S0 or S1is detected.
2 SBSO
I
O ISerial o~Dut of sub-code P -W.
I
41
I
WDCK O
D/A interface for 48-bit slot. Ward clock (f =
2FS).
H
42 LRCK O D/A interface for 48-bit slot, LR clock (f = FS).
43 LRCKI
I
i IlnDutsLR clock to DAC. (48-bit slot)
I 3 I EXCK I I lClack input for reading SBSO.
I
4
SQso
I
O Serial output of SUBQ (80-bit).
5
I
SQCK I
lCIOck in~~ for reacjina SQSO.
I
44
I
PCMD
I
O D/A interface. Serial data (2SCOMP, MBS first)
1 1 1
I
6
MUTE
I IIH] at muthg, [L]at muting cancel.
I
1 I
1
I
45
PCMDI
I Ilrmuts audio data to DAC. (48-bti slot)
I
I 7 I SENS I 0 ISENS signal outputto CPU.
I
I 46 I BCK I O lD/A interface, Bit clock.
I
8
XRST
I System reset, [L]at resetting.
9
DATA
I Inputs serial data from CPU.
10 XMT
I ~es inputfrom CPU. Serial data latches at falling
I 47 I
BCKI I I Ilnputs bit clock to DAC. (48-bit slot)
I
48 GTOP
1 GTOP signal output.
49 XUGF
o
XUGF signal output.
53
XPCK
o
XPCK
sgnal output.
51 GFS
o
GF.S
signal output.
9
RFCK
o
RF(X
signal output.
11
CLOK
I Inputs serial data transfer clock from CPU.
12 Vss
- CND. (OV)
13
SEIN
I Inputs SENS signalfrom SSP.
VSS I - IGND.
(OV)
I
14
CNIN
o Inputs track jump count signal.
1=1
15 DATO
o outputs serial data to SSP.
16 XLTO
o Ou#ts latches to SSP. Serial data latches at falling
54 C2P0 o
c2P0
signal output.
%
XROF
o
XRoF
signal output.
~
O 213diiided outputof pins 73 or 74.
17 CLKO
I Outputs serial data transfer clock to SSP.
18 SPQA I Interface for eXfension of M. processor (input A).
~
I Interface for eflension of M. processor (input B).
I Interface for extension of M. processor (input C).
I Crystal seiection L : 16.9344MHz, H : 33.8688MHz.
0 Interface for exlension of M. processor (output).
60 C4M o
4.2336
M-Iz O@p@
61 DOUT o
Digital out OUTPUT pin.
62 EMPH
o
Stays [H] for playback disc provided with
emphasis or [L]for that withoutemphasis.
23 FOK
1 Focus OK signal input pin. Used servo auto
sequena?r with SENS output.
24
MON
o ON/OFF control signal for spindle motor.
63
EMPHI
I
De-emphasis ON/OFF of DAC. [H] at ON, [L] a
OFF.
64
WFCK o
WFCK(Write Frame Clock) signal output.
25 I MDP I O I.Servo controlsignal for spindle motor.
I
26
MDS
I
O servo control signal for spindle motor.
I
E6
I
ZEROL
I
o Outputs detedon for non-sound data. [H] a
detection for non-sounddata (L-ch).
The oI@ti O! this pin is [H] when the GFS si nal
27 LOCK
8
0 sampled at 460 I+z is [H]. It turns ~] when the FS
signal turns out [L]8 or more times in succession.
I
6
I
ZEROR O
Outputs detection for non-sound data. [H] ~
detection for non-sound data (R-ch).
28
TEST
I Pin for TEST. Normal used stage: GND.
23
FILO
o Output of filter for master PLL. (Slave = Digital PLL)
30
FILI
I
Inputs to fitter for master PLL.
67
DTS1
I Test
pin for DAC. Normal used state: [L]
63 VDD
-
Power supply for DAC.
m
NLPWM
o
O@puts FWVM for L-ch. (Negative Phase)
31
Pco
o outputs of charge pump for master PLL.
32
VDD
- Power supply for digital. (+5V)
33
AVSS1
- Power supply for analog. (OV)
70 LPWN
o
Outputs PWM for L-ch. (Positive Phase)
71 AVDD2
-
Power supply for PWM driver.
i2 AVDD3
-
Power SUDDIVfor X’tal.
W I CLTV I I IVCO controlvoitage inputfor master PLL.
I I 73 I XIAl I I Ilnputs x’fal oscillation circuit (33.8688 MHz).
35
AVDD1
I
- Power supply for analog. (+5V)
261
RF I IEFM sianal inDljt.
I
I
74
I
XTAO
I
O Outputs X’tal oscillation circuit (33.8688 MHz).
75 AVSS3
- Power supply for Xtal. (GND)
m
AVSS2
- Power supply for PWM driver. (GND)
77 NRPWM
o
Outp@s W/b! for R-ch. (Negative Phase)
37
BIAS
1 Inputs constant current for asymmetry correction
circuit.
38
ASYI
, Inputscomparator voltage for asymmetry correction
circuit.
33
ASYO
o EFM fillswingoutput. ([L]= VSS, [H] = VDD)
40
ASYE
1 0-1 : OFF d asymmetly correction. [H] : ON O!
asymmetly correction.
78 RPWM
o
Outputs WIM for R-ch. (Positive Phase)
m
DST2
I Test
pin for DAC. Normal used state: [L]
m
DST3
I Test pin for DAC. Normal
USed state : [L]
-56-