Sharp CE-150 - Page 251

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Through th is li ne can be supplied t he clock 10 an external system since 1he clock in the
same ph;,sc as the CPU internal basic clock is on this line. C onn cc ci on of the 2.6M H1
crystal oscilla to r lo XLO and XLI will supp ly ihc cl ock of l .JMHz .
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Me 1n ory \Vri te si g rHtl. ./\ l o\v on th is lin e caus es th e C l> U t c> se nd dat a on L he d ata bus .
Q) OD
Ompul disable signal. A high on this line causes the CPU IO prohihi1 data ou1put 10 th e
external de v ice . It is used in \Vriting da ta ro the me rno ry.
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~AEOo f~
ME1 I
OD ~- -' '- ----- -~ - __,/
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00-07' ...... --- -~< MEMORY O ATA D >--- - < CPlJ DA TA ) >--- --
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k4 cmo 1y < cad c· ; cle
Men lO I'; ·1• ote e ye ~
©R ESET
C PU reset input. High stale or this si gnal 1·cscts the CPU and t he con1cn1s of 1h c
addre ss FFFEH is sci IO the register PH ;ind the contents of the addres s FFFFM lo the
rcgisier PL. When ii !ur ns from hi gh to low level. it si ar ts program execution from the
address or !he program counter.
CD NMI
Non1 -maskablc in1 cr rup1 input. High stale of this signal caus es in1crmp1 10 the CPU . to
\v hi ch the CPlJ uncondit i onaJJ y r es pond s a nd sta rt s the i nt e rrupt proc e ssing ro utin e of
which hi gh order byte addre ss is re pr esented by 1hc addr ess FFFC H and l ow order
byre addr ess by FFFD H.
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