Sharp CE-150 - Page 317

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CLI
SDI
no
3-4-4. Reset
0
234567
11 '1 se (ia1
recei ve
~ A'>~ ~~~~ ~ ~~~ ~ -'
1 R eset as it \vent
into seria l da ta
receive.
Reset as the
CPU read t he
seda 1 data.
Wh en the RES ET line is k ep t in .. , .. at least for three <IOS clock cyd cs . it causes internal
reset. by wh ic h all internal rcgi stcn< arc cleared to "0 " and ports PA and PB go into the
inp ut n1ode . · 111 e divider . hovic ve r. \ viii no t be r eset.
Term inal states after the reset ar c as s ho wn in Table below.
Pin name In /O ut Stace after reset
00- 01 l o/ Out High impedance
PAO -·PA7
.. ..
PBO - PB7
.. ..
l- PCO - PC7
Out I Lov: 1c ... e1
WAIT
..
( NO TE)
DMEO
.. ..
DMEt
.. ..
I NT
"
L0\•1 leve l
SDO
In/Out Hig h level
CLO
..
L o\•1 le\lel
NOTE : WAI T. DM EO. and OM Et are output dependent of WO. ME O, W1, and MEl and do no t
have any connection ,., it h reset.
77
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