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at
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4-2. PC-1500
4-2-1. Outline
(j)
CPU
The 1.H5801
CMO
S 8
-b
it Microprocessor is used. As it is
operated
by
the
clock
frequency
of
2.6M Hz from the crystal oscillator. its internal machine cycle is I .3M Hz.
BFI
...........
Depression
of
the
@!~
key
turn
s
it
to high level
so
that
YCC
is
supplied from
BFO.
INO~
I
N7
......
Input port for
other
t
ha
n the @ key.
DO
~
D7 .
.......
Bidirectional
dat<t
bus which is us
ed
to write
tm
d r
ead
dat
a to/ from
the
exter
nal rncrnory.
DO:
I.SB
07
: MSB
ADO·
v
ADl
5
...
.
Addr
ess bus.
ADO:
LSB
ADl5:
MSB
XLO.
XU
......
Ex
t
ern
al crystal
co
nn
ection terminals.
thr
ouJ;h w
hi
ch the 2.
6MHz
crystal is conn
ec
ted.
(j)
110
PC
XLO:
Inpu
t
XI.I:
Outpu
t
Either LH58
10
or
l..H581 I is used. The
sam
e chip is used fo r l/
Oof
CE-
15
0.
CE
-153.
and
CE
-1
58.
PAONPA7
.
..
. . Key s
tr
C
>IJc
output
Pll7 . . . . . . . . . . . @ key inpm
ADO
~
·J
.
A0
1
2~13.
Dtv)EI
......
Add
ress
of
1/ 0 port is set.
wi
thin
FOOOH
to
FOOFH
of
the
MEI
ar
ea.
0 Timer IC
µ PD 1990AC is used
and
co
nnected with
th
e 32.768kHz crystal.
© Chip
se
lect decoder
It
con
sists
of
two chips of TC4011 I
39F
and
TC
40H I 38F
and
it is used to
se
lect chip by
means of
so~
4.
S6.
S7
. 2Y2
and
2Y3. F
or
mo
re
details. r
efer
to
"C
hip select c
ir
cuit".
<D
Display chip
Because 4-bit SC882G is u
se
d. chip I
is
used in pa
ir
with
ch
ip 3 a nd chip 2
wi
th chip 4.
Select
si
gnal is co
mm
only us
ed
hy chip I
and
chip 3
or
chip 2
an
d chip 4. Data hus is
therefore divid
ed
into
DO
·vOJ a nd
04-
07
in
or
der to handle compatible with the 8-
hit
RAM.
Addr
ess
is
within 7600H
to
77FFH
of
the
MEO
ar
ea
and
is used
fo
r the
fi
xed variable
ar
ea.
in
addition
10
·1hc d
i:>p
lay buffer.
©System
ROM
It
is
the
PC-1500 syst
em
pr
ogram re
si
ding RO M
fo
r which the 8-bit X 1
6K
SC61328F
is u
se
d. Addre
ss
is
wi
thin
COOO
H to
FFFF
H
of
the
ME
O
ar
ea
.
0 System RAM
Because the 4-b
it
X I K bytes TC55
14
is
used in a pai
r.
the
data
bus
is divided
im
o t
woo
f
DO
-
DJ
and
D4- D7
and
the select signal S7 is c
ommo
nl
y sh
ar
ed
so
as to be
compat
ible with the 8-bit R
AM.
A
ddr
ess
is
wi
thin 7800H
to
7Bl'FH
of
the
MEO
a
re
a w
hi
ch is used for the system
memory area a
nd
for the fixed v
ar
i
ab
le
area
.
89
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